Buffer Descriptor Table - STMicroelectronics RM0365 Reference Manual

Universal serial bus full-speed device interface (USB)
32.6.2

Buffer descriptor table

Although the buffer descriptor table is located inside the packet buffer memory, its entries
can be considered as additional registers used to configure the location and size of the
packet buffers used to exchange data between the USB macro cell and the device.
On devices with "1 x 16 bits/word" access scheme, all packet memory locations are
accessed by the APB using 32-bit aligned addresses, instead of the actual memory location
addresses utilized by the USB peripheral for the USB_BTABLE register and buffer
description table locations.
In the following pages, two address locations are reported for devices with "1 x 16 bits/word"
access scheme: the one to be used by application software while accessing the packet
memory, and the local one relative to USB peripheral access. To obtain the correct memory
address value to be used in the application software while accessing the packet memory,
the actual memory location address must be multiplied by two.
On devices with "2 x 16 bits/word" access scheme, the address location to be used by
application software is the same as the local one relative to USB peripheral access. The
packet memory on these devices should be accessed only by byte (8-bit) or half-word (16-
bit) accesses. Word (32-bit) accesses are not allowed.
The first packet memory location is located at 0x4000 6000. The buffer descriptor table
entry associated with the USB_EPnR registers is described below.
A thorough explanation of packet buffers and the buffer descriptor table usage can be found
in Structure and usage of packet buffers on page
Transmission buffer address n (USB_ADDRn_TX)
Address offset ("1 x 16 bits/word" access scheme): [USB_BTABLE] + n*16
Address offset ("2 x 16 bits/word" access scheme): [USB_BTABLE] + n*8
USB local address: [USB_BTABLE] + n*8
Note: In case of double-buffered or isochronous endpoints in the IN direction, this address location
is referred to as USB_ADDRn_TX_0.
In case of double-buffered or isochronous endpoints in the OUT direction, this address
location is used for USB_ADDRn_RX_0.
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Bits 15:1 ADDRn_TX[15:1]: Transmission buffer address
Bit 0 Must always be written as '0 since packet memory is half-word wide and all packet buffers
must be half-word aligned.
Transmission byte count n (USB_COUNTn_TX)
Address offset ("1 x 16 bits/word" access scheme): [USB_BTABLE] + n*16 + 4
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ADDRn_TX[15:1]
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These bits point to the starting address of the packet buffer containing data to be transmitted
by the endpoint associated with the USB_EPnR register at the next IN token addressed to it.
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