Universal Serial Bus Full-Speed Device Interface (Usb); Introduction; Usb Main Features; Usb Implementation - STMicroelectronics RM0365 Reference Manual

RM0365
32

Universal serial bus full-speed device interface (USB)

32.1

Introduction

The USB peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported which allows to stop the device clocks for low-power
consumption.
32.2

USB main features

• USB specification version 2.0 full-speed compliant
•
Configurable number of endpoints from 1 to 8
• Up to 1024 bytes of dedicated packet buffer memory SRAM
•
Cyclic redundancy check (CRC) generation/checking, Non-return-to-zero Inverted
(NRZI) encoding/decoding and bit-stuffing
•
Isochronous transfers support
•
Double-buffered bulk/isochronous endpoint support
•
USB Suspend/Resume operations
•
Frame locked clock pulse generation
The following additional feature is also available depending on the product implementation
(see Section 32.3: USB
• USB 2.0 Link Power Management support
32.3

USB implementation

Table 170
Number of endpoints
Size of dedicated packet buffer memory SRAM
Dedicated packet buffer memory SRAM access
scheme
USB 2.0 Link Power Management (LPM) support
1. X= supported
2. When the CAN peripheral clock is enabled in the RCC_APB1ENR register, only the first
768 Bytes are available to USB while the last 256 Bytes are used by CAN.
3. The 512 bytes are totally available to USB; nothing is shared with CAN.
implementation):
describes the USB implementation in the devices.

Table 170. STM32F302xx USB implementation

(1)
USB features
DocID025202 Rev 7
Universal serial bus full-speed device interface (USB)
STM32F302x6/8/D/E
1024 bytes
2 x 16 bits / word
STM32F302xB/C
8 8
(2)
512 bytes
1 x 16 bits / word
X
(3)
-
1004/1080
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