Usb Registers; Common Registers - STMicroelectronics RM0365 Reference Manual

Advanced arm-based 32-bit mcus
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Universal serial bus full-speed device interface (USB)
32.6

USB registers

The USB peripheral registers can be divided into the following groups:
Common Registers: Interrupt and Control registers
Endpoint Registers: Endpoint configuration and status
Buffer Descriptor Table: Location of packet memory used to locate data buffers
All register addresses are expressed as offsets with respect to the USB peripheral registers
base address 0x4000 5C00, except the buffer descriptor table locations, which starts at the
address specified by the USB_BTABLE register. All register addresses are aligned to 32-bit
word boundaries although they are 16-bit wide. On devices with "1 x 16 bits/word" access
scheme, the same address alignment is used to access packet buffer memory locations,
which are located starting from 0x4000 6000.
Refer to
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).
32.6.1

Common registers

These registers affect the general behavior of the USB peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.
USB control register (USB_CNTR)
Address offset: 0x40
Reset value: 0x0003
15
14
13
CTR
PMAOVR
ERR
WKUP
M
M
M
rw
rw
rw
Bit 15 CTRM: Correct transfer interrupt mask
Bit 14 PMAOVRM: Packet memory area over / underrun interrupt mask
Bit 13 ERRM: Error interrupt mask
Bit 12 WKUPM: Wakeup interrupt mask
1019/1080
Section 2.1 on page 42
12
11
10
9
SUSP
RESET
SOF
M
M
M
M
rw
rw
rw
rw
0: Correct Transfer (CTR) Interrupt disabled.
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding bit in the
USB_ISTR register is set.
0: PMAOVR Interrupt disabled.
1: PMAOVR Interrupt enabled, an interrupt request is generated when the corresponding bit
in the USB_ISTR register is set.
0: ERR Interrupt disabled.
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
0: WKUP Interrupt disabled.
1: WKUP Interrupt enabled, an interrupt request is generated when the corresponding bit in
the USB_ISTR register is set.
for a list of abbreviations used in register descriptions.
8
7
6
ESOF
L1REQ
Res
M
M
.
RESUME
rw
rw
DocID025202 Rev 7
5
4
3
L1
RE
F
SUME
SUSP
MODE
rw
rw
rw
RM0365
2
1
0
LP_
PDW
F
N
RES
rw
rw
rw

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