Reference Arm® Documentation; Swj Debug Port (Serial Wire And Jtag) - STMicroelectronics RM0365 Reference Manual

RM0365
The ARM
•
SWJ-DP: Serial wire / JTAG debug port
•
AHP-AP: AHB access port
•
ITM: Instrumentation trace macrocell
•
FPB: Flash patch breakpoint
•
DWT: Data watchpoint trigger
•
TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
•
ETM: Embedded Trace Macrocell (available only on STM32F302xB/C devices larger
packages, where the corresponding pins are mapped)
It also includes debug features dedicated to the STM32F302xx:
•
Flexible debug pinout assignment
•
MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on the debug feature supported by the ARM
refer to the Cortex
Design Kit-r0p1 TRM (see
33.2 Reference ARM
•
Cortex-M4
It is available from: http://infocenter.arm.com
•
ARM
•
ARM
33.3

SWJ debug port (serial wire and JTAG)

The STM32F302xx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an
®
ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a
SW-DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
® ®
Cortex-M4 F core provides integrated on-chip debug support. It is comprised of:
®
-M4 with FPU-r0p1 Technical Reference Manual and to the CoreSight
Section 33.2: Reference ARM®
®
documentation
®
F r0p1 Technical Reference Manual (TRM)
®
Debug Interface V5
®
CoreSight Design Kit revision r0p1 Technical Reference Manual
DocID025202 Rev 7
Debug support (DBG)
® ®
Cortex-M4
documentation).
F core,
1038/1080
1066