Ppg0 To Ppg5 Output Control Registers (Ppg0/1, Ppg2/3, Ppg4/5) - Fujitsu F2MC-16LX Hardware Manual

17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3,
PPG4/5)
This section describes the configuration and functions of the PPG0 to PPG5 output
control registers (PPG0/1, PPG2/3, PPG4/5).
I PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/5)
The bit configuration of the PPG0 to 5 output control registers (PPG0/1, PPG2/3, PPG4/5) is
described below.
000040
H
000042
PCS2 PCS1 PCS0 PCM2 PCM1 PCM0
H
000044
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing
(0)
The functions of the bits in the PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/
5) are described below.
[Bits 7, 6, 5] PCS2 to 0:ppg Count Select (count clock selection)
These bits are used to select the operation clock for the down counter of channels 1, 3, and
5.
PCS2
0
0
0
0
1
1
• These bits are initialized to "000" at reset.
• Reading and writing are allowed.
Note:
In 8-bit prescaler/8-bit PPG mode and in 16-bit PPG mode, setting bits PCS2 to 0 is disabled
since the PPG of channels 1,3, and 5 receives the counter clock signal from channels 0,2,
and 4.
7 6 5 4
(0) (0) (0)
PCS1 PCS0
0 0
0 1
1 0
1 1
0 0
1 1
3 2 1 0
Reserved Reserved
(0) (0) (0) (0)
Operation mode
Peripheral device clock (62.5 ns machine clock for 16 MHz)
Peripheral device clock/2 (125 ns machine clock for 16 MHz)
Peripheral device clock/4 (250 ns machine clock for 16 MHz)
Peripheral device clock/8 (500 ns machine clock for 16 MHz)
Peripheral device clock/16 (1 µs machine clock for 16 MHz)
Input clock from the timebase counter
9
x 250 ns = 128 µs oscillation for 4 MHz)
(2
CHAPTER 17 8/16-BIT PPG TIMER
PPG0/1, PPG2/3, PPG4/5
Output control register
Initial value
339