Page 1 查询MB90580供应商捷多邦，专业PCB打样工厂，24小时加急出货 FUJITSU SEMICONDUCTOR CONTROLLER MANUAL MC-16LX 16-BIT MICROCONTROLLER MB90580 SERIES HARDWARE MANUAL...
Page 3 PREFACE Thank you for selecting FUJITSU Semiconductor Devices. The FUJITSU MB90580 series has been developed as one general-application version of the ® *16LX series of original 16-bit one-chip microcontrollers for ASIC (application specific IC) applications. This manual describes the functions and operations of the MB90580 series, and is intended for use by engineers actually designing products using these semiconductors.
Page 4 Chapter 12 COMMUNICATION PRESCALER This section describes the MB90580 series communication prescaler. Chapter 13 UART This section describes the function and operation of the MB90580 UART. Chapter 14 IE BUS This section describes the functions and operation of the MB90580 series IE Bus. Chapter 15 8/16-BIT PPG This section describes the functions and operation of the MB90580 series 8/16-bit PPG.
Page 5: Table Of Contents
CONTENTS Chapter 1 Overview ............................1 1.1 Features ............................1 1.2 Product Lineup ..........................3 1.3 Block Diagram ..........................4 1.4 Pin Assignment ..........................5 1.4.1 SQFP-100 Pin Assignment ....................5 1.4.1 QFP-100 Pin Assignment ......................6 1.5 Pin Functions ..........................7 1.6 Handling the Device ........................14 Chapter 2 CPU ..............................15 2.1 CPU ...............................15 2.1.1 Memory space ........................16 2.1.2 Registers ..........................20...
Page 6 6.4.3 Watch mode ........................69 6.4.4 Stop mode ...........................69 6.4.5 Hardware standby mode .....................70 6.4.6 CPU intermittent operation function ..................70 6.4.7 Setting the main clock oscillation stabilization waiting period ..........71 6.4.8 Switching the machine clock ....................71 6.4.9 State transition ........................73 Chapter 7 Interrupt ............................81 7.1 Outline ............................81 7.2 Causes of Interrupt ........................82 7.3 Interrupt Vector ..........................83...
Page 7 9.4 Operations ...........................112 9.4.1 External interrupts ......................112 9.4.2 DTP operation ........................113 9.4.3 Switching between external interrupt and DTP requests ...........114 9.5 Notes on use ..........................115 9.5.1 Conditions on the externally connected peripheral when DTP is used ......115 9.5.2 Recovery from standby ......................115 9.5.3 External interrupt/DTP operation procedure ..............115 9.5.4 External interrupt request level ..................115 Chapter 10 Delayed Interrupt Generation Module ..................117...
Page 8 13.3.6 Telegraph length set register (DEWR) ................152 13.3.7 Status register upper byte (STRH) ..................153 13.3.8 Status register lower byte (STRL) ...................155 13.3.9 Lock read register (LRRH, LRRL) ...................157 13.3.10 Master address read register (MARH, MARL) ...............158 13.3.11 Multiaddress, control bit read register (DCRR) ..............159 13.3.12 Telegraph length read register (DERR) .................160 13.3.13 Read data buffer (RDB) ....................161 13.3.14 Write data buffer (WDB) ....................162...
Page 9 16.3 Registers and Register Details ....................221 16.3.1 Control status registers (ADCS1 and ADCS2) ..............222 16.3.2 ADCR1 and ADCR0 (Data registers) ................226 16.4 Operations ..........................228 16.5 Notes on use ..........................234 16.5.1 Other considerations ......................234 Chapter 17 D/A Converter ..........................235 17.1 Outline ............................235 17.2 Block Diagram ...........................236 17.3 Registers and Register Details ....................237 17.3.1 DAT0/1 ( D/A data register) .....................238...
Page 10 21.2 Block Diagram ...........................291 21.3 Registers and Register Details ....................292 21.3.1 Program Address Detect Register 0/1 (PADR0/PADR1) ..........292 21.3.2 Program Address detect Control Status Register (PACSR) ..........293 21.4 Operations ..........................294 21.5 Application Example ........................295 Chapter 22 ROM Mirroring Module .......................299 22.1 Outline ............................299 22.2 Block Diagram ...........................299 22.3 Registers and Register Details ....................300...
Page 11 FIGURES Chapter 1 Overview ............................1 Figure 1.3a Block Diagram of MB90580 Series ..................4 Figure 1.4a Pin Assignment of MB90580 (LQFP-100)................5 Figure 1.4b Pin Assignment of MB90580 (QFP-100)................6 Figure 1.6a Using external clock ......................14 Figure 1.6b Connection of Power pins ....................14 Chapter 2 CPU ..............................15 Figure 2.1.1a Sample relationship between F2MC-16LX system and memory map ......
Page 12 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions ..........51 Figure 5.2a Watchdog Timer, Timebase Timer, and Watch Timer Block Diagram ......52 Figure 5.4.1a Watch-dog timer operation.................... 59 Chapter 6 Low Power Control Circuit ......................61 Figure 6.2a Low-power consumption control circuit and clock generator ........... 62 Figure 6.4.8a Clock Selection State Transition Diagram (1) ...............
Page 13 Chapter 12 UART ............................123 Figure 12.2a Block diagram of UART....................124 Figure 12.3a Registers of UART ....................... 125 Figure 12.4.3a Transfer data format (modes 0 and 1) ..............134 Figure 12.4.4a Transfer data format (mode 2) .................. 135 Figure 12.4.5a Timing to set PE, ORE, FRE, and RDRF (mode 0) ..........137 Figure 12.4.5b Timing to set ORE, FRE, and RDRF (mode 1) ............
Page 14 Figure 15.4.7a Counter State Transitions ..................218 Chapter 16 A/D Converter ..........................219 Figure 16.2a Block Diagram of A/D converter................... 220 Figure 16.3a Registers of A/D Converter ..................221 Figure 16.3.1a Control Status Registers ................... 222 Figure 16.3.2a Data Registers ......................226 Figure 16.4a Flow chart of A/D Conversion ..................
Page 15 Figure 22.2a Block Diagram of ROM Mirroring Module ..............299 Figure 22.3a Register of ROM Mirroring Module ................300 Figure 22.3b Memory in Single Chip Mode ..................301 Figure 22.3c Memory in Internal ROM External Bus Mode............... 301 Appendix A I/O Map ............................303 Appendix B Instructions ..........................309 Fig.
Page 16 MB90580 Series...
Page 17 TABLES Chapter 1 Overview ............................1 Table 1.2a MB90580 series product lineup ..................3 Table 1.5a Pin functions (1/4) (STBC: With standby control) ............7 Table 1.5b Pin functions (2/4) ......................8 Table 1.5c Pin functions (3/4) ......................9 Table 1.5d Pin functions (4/4) .......................10 Table 1.5e I/O circuit format (1) ....................11 Table 1.5f...
Page 18 Table 7.3a MB90580 interrupt assignment table (1/2) ..............83 Table 7.4.3a Compensation values for interrupt processing cycle count ........86 Table 7.6.2a ICS bits, channel numbers, and descriptor addresses ..........92 Table 7.6.2b S bits and end conditions ....................92 Table 7.6.2c Interrupt level setting bits and interrupt levels ............93 Table 7.6.4a Execution time when the extended I2OS continues ...........99 Table 7.6.4b...
Page 19 Table 14.4a Reload operation and pulse output ................201 Chapter 15 16-Bit Reload Timer (with Event Count Function) ..............207 Chapter 16 A/D Converter ..........................219 Chapter 17 D/A Converter ..........................235 Table 17.4a Theoretical values of D/A converter output voltages ..........239 Chapter 18 Pulse Width Counter (PWC) Timer ....................241 Table 18.4a Count Clock Selection ....................254 Table 18.4b...
Page 20 Table B.2.1k Normalize Instruction (Long-Word) (1 Instruction) ............327 Table B.2.1l Shift Instructions (Byte/Word/Long-Word) (18 Instructions) ........328 Table B.2.1m Branch 1 Instructions (31 Instructions) ..............329 Table B.2.1n Branch 2 Instructions (19 Instructions) ..............330 Table B.2.1o Other Control Instructions (Byte/Word/Long-Word) (36 Instructions) .......331 Table B.2.1p Bit Manipulation Instructions (22 Instructions) ............332 Table B.2.1q...
Page 21: Chapter 1 Overview
Chapter 1: Overview The MB90580 series 16-bit microcontrollers are designed for applications that require high-speed real-time processing. These microcontrollers feature functions that are suitable for controlling car audio and electronic appliances. 1.1 Features • Clock Embedded PLL Clock Multiplication Circuit Operating clock (PLL clock) can e selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz).
Page 22 1.1 Features • Timers 18-bit Timebase counter/watchdog timer: 1 channel Watch-dog timer : 1 channel 15-bit Watch timer : 1 channel 8/16-bit PPG timer: 8-bit × 2 channels or 16-bit × 1 channel 16-bit re-load timer: 3 channels 16-bit PWC timer (with noise filter) : 1 channel 16-bit I/O timer (16-bit free-run timer): 1 channel •...
Page 23: Product Lineup
1.2 Product Lineup 1.2 Product Lineup Internal Configuration Table 1.2a lists the product lineup of the MB90580 series. All products are functionally identical except for ROM and RAM sizes. Table 1.2a MB90580 series product lineup MB90V580 MB90583 MB90F583 ROM size ______ Mask ROM Flash ROM...
Page 24: Block Diagram
1.3 Block Diagram 1.3 Block Diagram X0,X1 Reset Circuit Clock control RSTX MC-16LX series core X0A,X1A circuit (Watch-dog timer) Hardware Standby circuit IEBUS™ HSTX Controller Timebase timer P00-07/AD00-07 Delayed Interrupt generator P10-17/AD08-15 P20-27/A16-23 P30/ALE Interrupt controller External P31/RDX P32/WRLX CMOS I/O PORT A PA0-2 P33/WRHX Interface...
Page 25: Pin Assignment
1.4 Pin Assignment 1.4 Pin Assignment 1.4.1 LQFP-100 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RSTX P22/A18 P23/A19 P24/A20 P97/POT P25/A21 P96/PWC P26/A22...
Page 26: Pin Assignment
1.4 Pin Assignment 1.4.1 QFP-100 Pin Assignment 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P20/A16 P21/A17 P22/A18 RSTX P23/A19 P24/A20 P25/A21 P97/POT P26/A22 P96/PWC P27/A23 P95/TOT2/OUT1 P30/ALE P94TOT1/OUT0 P31/RDX P93/TOT0/IN3...
Page 27: Pin Functions
1.5 Pin Functions 1.5 Pin Functions Table 1.5a to Table 1.5d lists the functions. Table 1.5e to Table 1.5g list the I/O circuit formats. Table 1.5a Pin functions (1/4) (STBC: With standby control) LQFP Pin name I/O Circuit Function Oscillator pin Oscillator pin HSTX Hardware standby input pin...
Page 28: Table 1.5B Pin Functions (2/4)
1.5 Pin Functions Table 1.5b Pin functions (2/4) LQFP Pin name I/O Circuit Function General-purpose I/O port SOT0 pin when the SOE bit of the UMC register is ’1’ Open drain output port when OD41 of the open drain control setting regis- ter (ODR4) is set to ’1’...
Page 29: Table 1.5C Pin Functions (3/4)
1.5 Pin Functions Table 1.5c Pin functions (3/4) LQFP Pin name I/O Circuit Function General-purpose I/O port Analog input pin (AN6) during A/D converter operation (CMOS/H) SCK4 UART4 serial data output (SOT4) pin General-purpose I/O port (CMOS/H) Analog input pins (AN7) during A/D converter operation 0.1uf capacitor connection pin for voltage supply stabilization.
Page 30: Table 1.5D Pin Functions (4/4)
1.5 Pin Functions Table 1.5d Pin functions (4/4) LQFP Pin name I/O Circuit Function General-purpose I/O port A pull-up resistor can be assigned (RD63=’1’) by using the pull-up resistor setting register (RDR6). (D63=’1’: Invalid when set as output) (CMOS/H) PPG00 PPG00 output when PPG is enabled General-purpose I/O port A pull-up resistor can be assigned (RD64=’1’) by using the pull-up resistor...
Page 31: Table 1.5E I/O Circuit Format (1)
1.5 Pin Functions Table 1.5e I/O circuit format (1) Class Circuit Remarks • Oscillation feedback resistor: 1 MΩ approx. Standby control signal • Hysteresis input with pull-up Resistor: 50 kΩ approx. • Hysteresis input port • With input pull-up resistor control •...
Page 32: Table 1.5F I/O Circuit Format (2)
1.5 Pin Functions Table 1.5f I/O circuit format (2) Class Circuit Remarks • CMOS level output • With open drain control • Hysteresis input with standby contro Open drain control signal Standby control signal • CMOS level output • Hysteresis input with standby control Standby control signal •...
Page 33: Table 1.5G I/O Circuit Format (3)
1.5 Pin Functions Table 1.5g I/O circuit format (3) Class Circuit Remarks • CMOS level output • Hysteresis input with standby control • Analog output • Shared with DA output DA Output Standby control signal • CMOS level output • Hysteresis input MB90580 series Chapter 1: Overview...
Page 34: Handling The Device
1.6 Handling the Device 1.6 Handling the Device (1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: A voltage higher than Vcc or lower than Vss is applied to an input or output pin. A voltage higher than the rated voltage is applied between Vcc and Vss. The AVcc power supply is applied before the Vcc voltage.
Page 35: Chapter 2 Cpu
Chapter 2: 2.1 CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high-speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing. In addition to 16-bit data, the F MC-16LX CPU core can process 32-bit data by using an internal 32-bit accumulator.
Page 36: Memory Space
2.1 CPU 2.1.1 Memory space Outline of CPU memory space An F MC-16LX CPU has a 16-Mbyte memory space. All data program input and output managed by the MC-16LX CPU are located in this 16-Mbyte memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus.
Page 37: Figure 2.1.1B Sample Linear Addressing
2.1 CPU Address generation types The F MC-16LX CPU has two address generation methods. One is the linear method in which an entire 24-bit address is specified by an instruction. The other method is the bank method in which the high-order eight bits of an address is specified by an appropriate bank register while the low-order 16 bits of the same address is specified by an instruction.
Page 38: Figure 2.1.1C Physical Addresses Of Each Space
2.1 CPU The 64-Kbyte bank specified by the PCB is called a program (PC) space. The PC space contains instruction codes, vector tables, and immediate value data, for example. The 64-Kbyte bank specified by the DTB is called a data (DT) space. The DT space contains readable/ writable data, and control/data registers for internal and external resources.
Page 39: Figure 2.1.1D Sample Allocation Of Multi-Byte Data In Memory
2.1 CPU Multi-byte data allocation in memory space Figure 2.1.1d is a diagram of multi-byte data configuration in memory. The low-order eight bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. 01010101 11001100 11111111...
Page 40: Registers
2.1 CPU 2.1.2 Registers The F MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and their applications are limited by the CPU architecture. The general-purpose registers share the CPU address space with RAM.
Page 41: Figure 2.1.2B General-Purpose Registers
2.1 CPU General-purpose registers The F MC-16LX general-purpose registers are located from addresses 000180H to 00037FH (maximum configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.1.2b.
Page 42: Figure 2.1.2D 32-Bit Data Transfer
2.1 CPU Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL). The A register is used as a temporary storage for operation results and transfer data. During 32-bit data processing, AH and AL are used together.
Page 43: Figure 2.1.2F Stack Manipulation Instruction And Stack Pointer
2.1 CPU User stack pointer (USP) and system stack pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data in the event of a push/pop instruction or subroutine execution. The USP and SSP registers are used by stack instructions.
Page 44: Figure 2.1.2G Ps Structure
2.1 CPU Processor status (PS) The PS register consists of the bits controlling the CPU Operation and the bits indicating the CPU status. As shown in Figure 2.1.2g, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
Page 45: Figure 2.1.2I Register Bank Pointer
2.1 CPU (2) Register bank pointer (RP) The RP register indicates the relationship between the general-purpose registers of the F2MC-16LX and the internal RAM addresses. Specifically, the RP register indicates the first memory address of the currently used register bank in the following conversion expression: [00180H + (RP)*10H] (see Figure 2.1.2i).
Page 46: Table 2.1.2B Register Functions
2.1 CPU Register bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers. Table 2.1.2b lists the functions of the registers.
Page 47: Figure 2.1.2K Generating A Physical Address In Direct Addressing Mode
2.1 CPU Program counter bank register (PCB) <Initial value: Value in reset vector> Data bank register(DTB) <Initial value: 00H> User stack bank register(USB) <Initial value: 00H> System stack bank register(SSB) <Initial value: 00H> Additional data bank register(ADB) <Initial value: 00H> Each bank register indicates the memory bank where the PC, DT, SP (user), SP (system), or AD space is allocated.
Page 48: Prefix Codes
2.1 CPU 2.1.3 Prefix codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. Bank select prefix The memory space used for accessing data is determined for each addressing mode.
Page 49: Figure 2.1.3A Interrupt Disable Instruction
2.1 CPU Common register bank prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value. When CMR is placed before an instruction that accesses a register bank, that instruction accesses the common bank (the register bank selected when RP=0) at addresses from 000180H to 00018FH regardless of the current RP value.
Page 50: Figure 2.1.3B Interrupt Disable Instructions And Prefix Codes
2.1 CPU Restrictions on interrupt disable instructions and prefix instructions When a prefix code is placed before an interrupt disable instruction, the prefix code affects the first instruction after the code other than the interrupt disable instruction. Interrupt disable instruction •...
Page 51: Chapter 3 Memory
Chapter 3: Memory 3.1 Memory Access Modes In the F MC-16LX, there are several modes for access methods, access areas, and test methods. In this module, the following classifications apply: Table 3.1a Memory Access Mode Access Mode Operation Mode Bus Mode (External data bus width) Single Chip ———...
Page 52: Mode Pins
3.1 Memory Access Modes 3.1.1 Mode pins Table 3.1.1a describes the operations specified by combinations of the MD2 to MD0 external pins. Table 3.1.1a Mode pins and modes External Mode pin setting Reset vector Mode name data bus Remarks MD2 MD1 MD0 access area width 0 0 0...
Page 53: Mode Data
3.1 Memory Access Modes 3.1.2 Mode data Mode data is stored at FFFFDF of main memory and used for controlling the CPU operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence.
Page 54: Bus Mode
3.1 Memory Access Modes 3.1.3 Bus Mode Figure 3.1.3a shows correspondence between the access areas and physical addresses for each bus mode. FFFFFF Address #1 FE0000 010000 (FF bank image) (FF bank image) Address #2 004000 002000 Address #3 : No access : Internal access 000100 0000C0...
Page 55: Chapter 3 Memory
3.1 Memory Access Modes Recommended setting Table 3.1.3a lists a sample recommended setting of mode pins and mode data. Table 3.1.3a Sample recommended setting of mode pins and mode data Sample setting × Single chip Internal ROM and external bus mode, 16-bit bus Internal ROM and external bus mode, 8-bit bus External ROM and external bus mode, 16-bit bus, vector 16 bus width External ROM and external bus mode, 8-bit bus...
Page 56: External Memory Access
3.2 External Memory Access 3.2 External Memory Access To access external memory and peripherals, the F MC-16LX supplies the following address, data, and control signals: (P37) Machine cycle clock (KBP) (P36) External ready input pin WRHX (P33) : Write signal for high-order 8 bits of data bus WRLX (P32) Write signal for low-order 8 bits of data bus...
Page 57: Registers And Register Details
3.2 External Memory Access 3.2.2 Registers and Register details Automatic ready function selection register Bit No. Address: 0000A5 — — IOR0 IOR1 HMR1 HMR0 LMR1 LMR0 ARSR Read/write Initial value External address output control register Bit No. Address: 0000A6 HACR Read/write Initial value Bus control signal selection register...
Page 58 3.2 External Memory Access 3.2.2.1 Automatic ready function selection register Bit No. Address: 0000A5 IOR0 ARSR IOR1 HMR1 HMR0 LMR1 LMR0 Read/write Initial value [bits 15 and 14]: IOR1 and IOR0 These bits specify the automatic wait function for external access to the area between 000000 0000FF IOR1 IOR0...
Page 59: Table 3.2.0A Selecting The High-Order Address Bit Output Control
3.2 External Memory Access 3.2.2.2 External address output control register Bit No. Address: 0000A6 HACR Read/write Initial value This register controls the external output of addresses (A19 to A16). The bits corresponds to addresses A19 to A16, controlling the address output pins as described below. Table 3.2.0a Selecting the high-order address bit output control The corresponding pin is used as an address output (Axx).
Page 60 3.2 External Memory Access 3.2.2.3 Bus control signal selection register Bus control signal selection register Bit No. Address: 0000A7 — IOBS HMBS LMBS ECSR Read/write Initial value This register is used to set the bus control function in external bus mode. This register cannot be accessed when the device is in single chip mode.
Page 61 3.2 External Memory Access [bit 11]: HMBS This bit specifies the bus size when an area between 800000 and FFFFFF is externally accessed in 16-bit external data bus mode. The size is controlled as described below. 16-bit bus size access [default in mode other than external vector mode 2] 8-bit bus size access [default in external vector mode 2] This bit is initialized to ’1’...
Page 62: Operations
3.2 External Memory Access 3.2.1 Operations MB90580 has a variety of access method and access area modes. See Section 3.1 ,“Memory Access Modes” (1) External memory access control signals External memory is accessed in three cycles while the ready function is not used. Figure 3.2.4 shows the concept of external access timing.
Page 63: Figure 3.2.1B External Memory Access Timing Chart
3.2 External Memory Access External 16-bit bus mode 8-bit bus width byte 8-bit bus width byte read write Even-number address Even-number address byte read byte write P37/CLK P33/WRHX P32/WRLX P31/RDX P30/ALE Read Read address P27 to 20/A23 to16 Write address address Read Write...
Page 64: Figure 3.2.1C Ready Timing Chart
3.2 External Memory Access (2) Ready function When the RYE bit of the bus control signal selection register (EPCR) is set to ’1,’ a wait cycle is inserted while an L level signal appears at the R36/RDY pin in the event of an access to an external area. Thus, the access cycle can be extended.
Page 65: Figure 3.2.1D Hold Timing
3.2 External Memory Access When the RYE bit of EPCR is set to ’1,’ the wait cycle continues if an L level signal appears at the R36/RDY pin at the end of either automatic ready cycle. (3) Hold function When the HDE bit of EPCR is set to ’1,’ the external bus hold function by the P34/HRQ and P35/HAKX pins is enabled.
Page 67: Chapter 4 Clock And Reset
Chapter 4: Clock and Reset 4.1 Clock Generator The clock generator controls internal clock operation, including such functions as sleep, timer, stop, and PLL multiplication. This internal clock is called the machine clock, and one cycle of the machine clock is called a machine cycle.
Page 68: Reset Causes
4.2 Reset Causes 4.2 Reset Causes When a reset cause occurs, F MC-16LX terminates the currently executing processing and waits for the release of reset signal. A reset can be caused by the following factors: Power-on reset Hardware standby release Watch-dog timer overflow External reset request via RSTX pin Reset request by software...
Page 69: Figure 4.2A Reset Cause Bit Block Diagram
4.2 Reset Causes HSTX pin RSTX pin HSTX=LÆH RSTX=L Without periodic clear Power on RST bit set Hardware standby External reset Power-on Watch-dog timer STBYC.RST bit release detection request detection reset detection circuit detection circuit write detection circuit circuit circuit WTC register Delay F / F...
Page 70: Operation After Reset Release
When using the F MC-16LX in single chip mode or internal ROM external bus mode, Fujitsu recommends specifying internal vector mode. The bus mode after the reset vector and mode data are read is specified by the mode data.
Page 71: Chapter 5 Watchdog Timer, Timebase Timer, And Watch Timer Functions
Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions 5.1 Outline Watch-Dog Timer The watchdog timer consists of 2-bit counter that uses to carry signal from the 18-bit timebase timer or the 15-bit watch timer as a clock source, a control register, and a watchdog reset controller. The watch-dog timer function enables detection of program surge.
Page 72: Block Diagram
5.2 Block diagram 5.2 Block diagram Main clock TBTC Clock input TBC1 Selector Timebase timer TBC0 TBTRES TBIE TBOF Timebase interrupt WDTC Watchdog reset 2-bit counter generation circuit Selector To WDGRST internal reset generation circuit WDCS Power-on reset /subclock stop WTC1 Selector Watch timer...
Page 73: Registers And Register Details
5.3 Registers and register details 5.3 Registers and register details Watch-Dog timer control register Bit number Address : 0000A8 ERST SRST PONR STBR WRST WDTC Read/write Initial value Timer base timer control register Bit number Address: 0000A9 Reserved TBTC TBIE TBOF TBC1 TBC0...
Page 74: Wdtc (Watch-Dog Timer Control Register)
5.3 Registers and register details 5.3.1 WDTC (Watch-Dog Timer Control Register) Watch-Dog timer control register Bit number Address : 0000A8 ERST SRST PONR STBR WRST WDTC Read/write Initial value Don’t use read-modify-write command to access this register, otherwise malfunction will occur. [bits 7 to 3] PONR, STBR, WRST, ERST, and SRST These flags indicate the reset causes.
Page 75: Table 5.3.1B Watchdog Timer Interval Selection Bits
5.3 Registers and register details Table 5.3.1b Watchdog Timer Interval Selection Bits Interval Time (Source oscillation: 4 MHz) WDCS/ Minimum Maximum Approx. 3.58 ms Approx. 4.61 ms Approx. 14.33 ms Approx. 18.43 ms Approx. 57.23 ms Approx. 73.73 ms Approx. 458.75 ms Approx.
Page 76: Tbtc (Time Base Timer Control Register)
5.3 Registers and register details 5.3.2 TBTC (Time Base Timer Control Register) Timer base timer control register Bit number Address: 0000A9 Reserved TBIE TBOF TBC1 TBC0 TBTC Read/write (R/W) (R/W) (R/W) (R/W) Initial value Note: Don’t use read-modify-write command to access this register, otherwise malfunction will occur.
Page 77: Watch Timer Control Register (Wtc)
5.3 Registers and register details 5.3.3 Watch Timer Control Register (WTC) Watch timer control register Bit number Address: 0000AA WDCS WTIE WTOF WTC2 WTC1 WTC0 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [Bit 7] WDCS This bit selects whether to use the clock signal from the watch timer or from the timebase timer for the watchdog timer input clock when the main clock and PLL clock are selected.
Page 78: Table 5.3.3A Watch Timer Interval Selection
5.3 Registers and register details Table 5.3.3a Watch Timer Interval Selection Interval time when WTC2 WTC1 WTC0 subclock is 32 kHz 15.625 ms 31.25 ms 62.5 ms 0.125 s 0.250 s 0.500 s 1.000 s – Chapter 5: Watchdog Timer, Timebase Timer, and Watch Timer Functions MB90580 Series...
Page 79: Operation
5.4 Operation 5.4 Operation 5.4.1 Watch-Dog Timer The watch-dog timer function enables detection of program surge. If the watch-dog timer is not accessed within the specified time due to, for example, a program surge, the watch-dog timer resets the system. (1) Activation The watch-dog timer is activated by writing ’0’...
Page 80: Time Base Timer
5.4.2 Time Base Timer The time base timer functions as a watch-dog timer clock source, timer for waiting for the oscillation to sta- bilize, and interval timer for generating interrupts at specified intervals. (1) Time base counter The time base counter consists of an 18-bit counter for a clock generated by dividing the source oscillation input by two.
Page 81: Chapter 6 Low Power Control Circuit
Chapter 6: Low Power Control Circuit 6.1 Outline The following are the operating modes: PLL clock mode, PLL sleep mode, PLL watch mode, pseudo-watch mode, main clock mode, main sleep mode, main watch mode, main stop mode, subclock mode, sub sleep mode, sub watch mode, sub stop mode, and hardware standby mode. Aside from the PLL clock mode, all of the other operating modes are low power consumption modes.
Page 82: Block Diagram
6.2 Block Diagram 6.2 Block Diagram CKSCR Subclock Subclock switching (OSC oscillation) controller CKSCR Main clock PLL multiplier circuit (OSC oscillation) CPU system clock generation CPU clock CKSCR 1/2 S 0/9/17/33 intermittent cycle selection CPU clock selector LPMCR CPU intermittent operation function cycle number selection circuit...
Page 83: Registers And Register Details
6.3 Registers and register details 6.3 Registers and register details Clock selection register Bit No. Address: 0000A1 CKSCR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Low power mode control register Bit No. Address: 0000A0 LPMCR Read/write (R/W) (R/W) (R/W) (R/W) Initial value...
Page 84: Table 6.3.1A Cg Bit Setting
6.3 Registers and register details [Bit 4] RST Writing a "0" to this bit generates an internal reset signal in three machine cycles. Writing a "1’ to this bit has no effect. When this bit is read, a "1" is returned. [Bit 3] TMD Writing a "0"...
Page 85: Ckscr (Clock Selection Register)
6.3 Registers and register details 6.3.2 CKSCR (Clock selection register) Clock selection register Bit No. Address: 0000A1 CKSCR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [Bit 15] SCM This bit indicates whether the main clock or the subclock is selected as the machine clock. When this bit is "0", it indicates that the subclock is selected;...
Page 86: Table 6.3.2B Cs Bit Settings
6.3 Registers and register details [Bit 10] MCS This bit selects either the main clock or the PLL clock as the machine clock. When a "0" is written to this bit, the PLL clock is selected; when a "1" is written to this bit, the main clock is selected. If a "0" is written to this bit while it is "1", the oscillation stabilization waiting period for the PLL clock is generated;...
Page 87: Operations
6.4 Operations 6.4 Operations The status of each chip block in each operating mode is shown in Table 6.4a Table 6.4a Low Power Consumption Mode Operating Statuses Transition Main Peripheral Exit Clock Pins condition oscillation oscillation method SCS=0 Reset Subclock Operating Stopped Operating...
Page 88: Sleep Mode
6.4 Operations 6.4.1 Sleep mode Transition to sleep mode The standby control circuit is set to sleep mode by writing a "1" to the SLP bit, a "1’ to the TMD bit, and a "0" to the STP bit in the low power consumption mode control register. In sleep mode, only the clock sup- plied to the CPU is stopped;...
Page 89: Watch Mode
6.4 Operations processing resumes from the instruction that follows the last instruction that put the device into pseudo-watch mode. 6.4.3 Watch mode Transition to watch mode The standby control circuit is set to watch mode by writing a "0" to the TMD bit in the low power con- sumption mode control register.
Page 90: Hardware Standby Mode
6.4 Operations Exiting stop mode The standby control circuit releases stop mode when a reset signal is input or when an interrupt is generated. If stop mode was released by a reset source, the device enters the reset state after stop mode is released.
Page 91: Setting The Main Clock Oscillation Stabilization Waiting Period
6.4 Operations In addition, the instruction execution time when the CPU intermittent operation function is used can be calculated by adding a compensation factor (the number of register, on-chip memory, on-chip resource, and external bus access multiplied by the number of pause cycles) to the normal execution time. Peripheral clock CPU clock Intermittent operation pause cycle...
Page 92: Figure 6.4.8A Clock Selection State Transition Diagram (1)
6.4 Operations Machine clock initialization The MCS bit and the SCS bit are not initialized by a reset caused by an external pin or the RST bit. After other types of resets, these bits are each initialized to "1". Figure 6.4.8a and Figure 6.4.8b show the clock selection state diagram. Power on ⇒...
Page 93: State Transition
6.4 Operations Power on ⇒ Main Main SCS=1, MSC=1 SCS=0 SCM=1 SCM=1 MCM=1 MCM=1 ⇒ ⇒ PLLx Main SCS=0, MSC=x SCS=1 SCS=0 SCM=1,MCM=0 SCM=0 SCM=0 CS1/0=xx MCM=1 MCM=1 ⇒ Main PLLx (1) SCS bit clear SCS=1, MSC=0 (2) Subclock edge detection timing SCM=1, MCM=1 CS1/0=xx (3) SCS bit set...
Page 94: Table 6.4.9A List Of Transition Conditions
6.4 Operations MCS: MCS bit (clock selection register) (PLL clock mode is selected when MCS = 0) SCS: SCS bit (clock selection register) (sub-clock mode is selected when SCS = 0) STP: STP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) SLP: SLP bit (low power consumption mode register) (sleep mode is selected when SLP = 0) TMD:...
Page 95 6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition Transition conditions State after transition 02 Main oscillation stabilization waiting period completed Main mode Main oscillation stabiliza- 03 Reset initiated or interrupt tion 04 SCS = 0 written Sub mode SM transition mode 27 TMD = 1•STP = 0•SLP = 1 written...
Page 96: Chapter 7 Interrupt
6.4 Operations Table 6.4.9a List of Transition Conditions (Continued) State before transition Transition conditions State after transition 49 Main → sub-clock switching timing wait completed Sub-sleep MS transition sleep 50 Interrupt or reset initiated MS transition mode 54 PLL → main clock switching timing wait completed MS transition sleep PS transition sleep 55 Interrupt or reset initiated...
Page 97: Figure 6.4.9A Low Power Consumption Mode Transition Diagram A
6.4 Operations State Transition Diagrams Power-on reset SM transition mode Main oscillation SCS=1, MCS=1, SCS=1, MCS=1, stabilization period STP=0, SLP=0, STP=0, SLP=0, SCS=1, MCS=1, TMD=1 TMD=1 STP=0, SLP=0, SCM=1, MCM=1, SCM=0, MCM=1, TMD=1 SCD=0, MCD=0, SCD=0, MCD=0, SCM=1, MCM=1, PCD=1 PCD=1 SCD=0, MCD=0, PCD=1...
Page 98: Figure 6.4.9B Low Power Consumption Mode Transition Diagram B
6.4 Operations Main sleep SM transition sleep SCS=1, MCS=1, SCS=1, MCS=1, STP=0, SLP=1, STP=0, SLP=1, TMD=1 TMD=1 SCM=0, MCM=1, SCM=1, MCM=1, SCD=0, MCD=0, SCD=0, MCD=0, PCD=1 PCD=1 Main watch Main mode SM transition mode SCS=1, MCS=1, SCS=1, MCS=1, SCS=1, MCS=1, STP=0, SLP=0, STP=0, SLP=0, STP=0, SLP=0,...
Page 99: Figure 6.4.9C Low Power Consumption Mode Transition Diagram C
6.4 Operations Sub mode Sub oscillation Main oscillation SCS=0, MCS=x, stabilization time stabilization time STP=0, SLP=0, SCS=0, MCS=x, SCS=1, MCS=x, TMD=1 STP=0, SLP=0, STP=0, SLP=0, SCM=0, MCM=1, TMD=1 TMD=1 SCD=0, MCD=1, SCM=0, MCM=1, SCM=1, MCM=1, PCD=1 SCD=0, MCD=1, SCD=0, MCD=0, PCD=1 PCD=1 Sub sleep...
Page 100: Figure 6.4.9D Low Power Consumption Mode Transition Diagram D
6.4 Operations PLL mode Pseudo-watch Pseudo-watch SCS=1, MCS=0, transition mode STP=0, SLP=0, SCS=1, MCS=0, SCS=1, MCS=0, TMD=1 STP=1, SLP=0, STP=1, SLP=0, SCM=1, MCM=0, TMD=1 TMD=1 SCD=0, MCD=0, SCM=1, MCM=1, SCM=1, MCM=1, PCD=0 SCD=0, MCD=0, SCD=0, MCD=0, PCD=0 PCD=1 PLL sleep PLL watch SCS=1, MCS=0, transition P...
Page 101: Chapter 7 Interrupt
Chapter 7: Interrupt 7.1 Outline The F MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: Hardware interrupt: ........Interrupt processing due to an internal resource event Software interrupt: ........
Page 102: Causes Of Interrupt
7.2 Causes of Interrupt 7.2 Causes of Interrupt Table 7.2a Interrupt causes, interrupt vectors, and interrupt control registers Interrupt vector Interrupt control register IIOS Interrupt cause clear Number Address Number Address × Reset FFFFDC # 08 —— —— × INT9 instruction FFFFD8 # 09 ——...
Page 103: Interrupt Vector
7.3 Interrupt Vector 7.3 Interrupt Vector Table 7.3a MB90580 interrupt assignment table (1/2) Software interrupt Mode Interrupt Vector address L Vector address M Vector address H Hardware interrupt instruction register FFFFFC FFFFFD FFFFFE None INT 0 Unused FFFFE0 FFFFE1 FFFFE2 None INT 7 Unused...
Page 104: Hardware Interrupt
7.4 Hardware Interrupt 7.4 Hardware Interrupt 7.4.1 Overview In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function.
Page 105: Figure 7.4.3A Occurrence And Release Of Hardware Interrupt
7.4 Hardware Interrupt updates the ILM of PS to a level value of the received interrupt, sets the S flag, then performs branch processing. As a result, the interrupt processing program defined by the user is executed next. Figure 7.4.3a illustrates the flow from the occurrence of a hardware interrupt until there is no interrupt request in the interrupt processing program.
Page 106: Figure 7.4.3B Hardware Interrupt Operation Flow
7.4 Hardware Interrupt The time required for the CPU to execute the interrupt processing in steps is shown below. Interrupt start 24 + 6 x Table 7.4.3a machine cycles Interrupt return 15 + 6 x Table 7.4.3a machine cycles (RETI instruction) Table 7.4.3a Compensation values for interrupt processing cycle count Address indicated by the stack pointer Cycle count compensation value...
Page 107: Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed
7.4 Hardware Interrupt 7.4.4 Hardware Interrupt Ocurrence When Internal Resource Is Being Accessed When internal I/O area is being asscessed, the CPU will not response to hardware interrupt immediately, there will be one instruction delay. Please refer to Chapter 2, section 2.1.3 for details. 7.4.5 Interrupt Inhibit Instruction If F MC-16LX is executing interrupt inhibit instructions, the CPU will not response to hardware interrupt...
Page 108: Software Interrupt
7.5 Software Interrupt 7.5 Software Interrupt 7.5.1 Overview In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function.
Page 109: Operation
7.5 Software Interrupt 7.5.3 Operation When the CPU fetches and executes the software interrupt instruction, the software interrupt processing microcode is activated. The software interrupt processing microcode saves 12 bytes (PS, PC, PCB, DTB, ADB, DPR, and A) to the memory area indicated by SSB and SSP. The microcode then fetches three bytes of interrupt vector and loads them onto PC and PCB, resets the I flag, and sets the S flag.
Page 110: Extended Intelligent I/O Service (Ei2Os)
7.6 Extended intelligent I/O service (EI2OS) 7.6 Extended intelligent I/O service (EI 7.6.1 Overview OS is a type of hardware interrupt operation that automatically transfers data between I/O and memory. Conventionally, data is transferred between I/O and memory by an interrupt processing program. EI however, enables data to be transferred as if in DMA mode.
Page 111: Structure
7.6 Extended intelligent I/O service (EI2OS) 7.6.2 Structure OS is handled by the following four sections: Internal resources ....Interrupt enable and request bits: Used to control interrupt requests from resources. Interrupt controller ICR:Assigns interrupt levels, determines the priority levels of simultaneously requested interrupts, and selects the OS operation.
Page 112: Table 7.6.2A Ics Bits, Channel Numbers, And Descriptor Addresses
7.6 Extended intelligent I/O service (EI2OS) [bits 15 to 12] or [bits 7 to 4] ICS3 to ICS0 These bits are used to select the EI OS channel. These bits are write-only. The value specified in these bits determines the address of the extended intelligent I/O service descriptor in memory, which is explained later.
Page 113: Table 7.6.2C Interrupt Level Setting Bits And Interrupt Levels
7.6 Extended intelligent I/O service (EI2OS) [bit 11] or [bit 3] ISE This is the EI OS enable bit. This bit can be read or written to. Upon issuance of an interrupt request, OS is activated if this bit is set to ’1’ and the interrupt sequence is activated if this bit is set to ’0.’ If the EI OS end condition is satisfied (the S1 and S0 bits are not ’00’), the ISE bit is cleared to ’0.’...
Page 114: Figure 7.6.2A Extended Intelligent I/O Service Descriptor Configuration
7.6 Extended intelligent I/O service (EI2OS) (2)Extended intelligent I/O service descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100 and 00017F in internal RAM, and consists of the following items: Data transfer control data Status data Buffer address pointer Figure 7.6.2a shows the configuration of the extended intelligent I/O service descriptor.
Page 115 7.6 Extended intelligent I/O service (EI2OS) I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer to and from the buffer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000 and 00FFFF can be specified.
Page 116 7.6 Extended intelligent I/O service (EI2OS) [bit 1] DIR: Specify the data transfer direction. I/O → Buffer Buffer → I/O [bit 0] SE: Control the termination of the extended intelligent I/O service based on resource requests. The extended intelligent I/O service is not terminated by a resource request.
Page 117: Operation
7.6 Extended intelligent I/O service (EI2OS) 7.6.3 Operation Buffer address pointer I/OA I/O address pointer OS descriptor ISCS OS status Data counter OS enable bit Interrupt request issued S1 and S0 : OS end status from internal resource ISE = 1 Interrupt sequence Reading ISD/ISCS End request from resource...
Page 118: Figure 7.6.3B Ei2Os Use Flow
7.6 Extended intelligent I/O service (EI2OS) Processing by CPU Processing by EI2OS OS initialization Normal (Interrupt request) termination AND (ISE = 1) JOB execution Data transfer Re-setting of extended intelligent I/O service (Switching channels) Processing data in buffer Figure 7.6.3b EI OS use flow Chapter 7: Interrupt MB90580 Series...
Page 119: Ei2Os Execution Time
7.6 Extended intelligent I/O service (EI2OS) 7.6.4 EI OS Execution Time (1) When data transfer continues (when the stop condition is not satisfied) EI2OS Execution Time = (value in Table 7.6.4a + value in Table 7.6.4b) machine cycle Table 7.6.4a Execution time when the extended I2OS continues ISCS SE bit Set to ’0’...
Page 120: Exceptions
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing only for debugging or for activating emergency recovery software.
Page 121: Chapter 8 Parallel Ports
Chapter 8: Parallel Ports 8.1 Outline In MB90580 series, there are 10 parallel ports which are as follows: • Port 0 (8 CMOS I/O pins) • Port 1 (8 CMOS I/O pins) • Port 2 (8 CMOS I/O pins) • Port 3 (8 CMOS I/O pins) •...
Page 122: Block Diagram
8.2 Block Diagram 8.2 Block Diagram Internal data bus Data register read Data register Data register write Direction register Direction register write Direction register read Figure 8.2a Block diagram of I/O port Internal data bus Pull-up resistor (about 50 kΩ) Data register Direction register Resistor register...
Page 123: Registers And Register Details
8.3 Registers and register details 8.3 Registers and register details 15/7 14/6 13/5 12/4 11/3 10/2 Address : 000000 Port 0 data register (PDR0) Address : 000001 Port 1 data register (PDR1) Address : 000002 Port 2 data register (PDR2) Address : 000003 Port 3 data register (PDR3) Address : 000004...
Page 124: Port Data Register
8.3 Registers and register details 8.3.1 Port data register Initial value Access PDR0 xxxxxxxx Address: 000000 PDR1 xxxxxxxx Address: 000001 PDR2 xxxxxxxx Address: 000002 PDR3 xxxxxxxx Address: 000003 PDR4 xxxxxxxx Address: 000004 PDR5 xxxxxxxx Address: 000005 PDR6 --xxxxxx Address: 000006 PDR7 ---xxxx- Address: 000007...
Page 125: Port Direction Registers
8.3 Registers and register details 8.3.2 Port direction registers Initial value Access DDR0 00000000 Address: 000010 DDR1 00000000 Address: 000011 DDR2 00000000 Address: 000012 DDR3 00000000 Address: 000013 DDR4 00000000 Address: 000014 DDR5 00000000 Address: 000015 DDR6 --000000 Address: 000016 DDR7 - - - 0000- Address: 000017...
Page 126: Output Pin Register
8.3 Registers and register details 8.3.3 Output pin register Port 4 pin register Bit number Address : 00001B OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 ODR4 Read/write Initial value This register controls the open drain in output mode. Standard output port in output mode [initial value] Open drain output port in output mode Note: This register is not used in input mode.
Page 127: Analogue Input Enable Register
8.3 Registers and register details 8.3.5 Analogue Input Enable Register Port 5 analogue enable register Bit number Address : 00001C ADER ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Read/write Initial value This register controls the .behaviour of port 5. Port input mode Analogue input mode [initial value]...
Page 128 8.3 Registers and register details [bit 9] - LN9 controls Port 9 Normal output buffer [initial value] Low noise output buffer [bit 8] - LN8 controls Port 8 Normal output buffer [initial value] Low noise output buffer [bit 7] - LN7 controls Port 7 Normal output buffer [initial value] Low noise output buffer...
Page 129: Chapter 9 Dtp/External Interrupt
Chapter 9: DTP/External Interrupt 9.1 Outline The DTP (Data Transfer Peripheral) is a peripheral block that interfaces external peripherals to the MC-16LX CPU. The DTP receives DMA and interrupt processing requests from external peripherals and passes requests to the F MC-16LX CPU to activate the extended intelligent I/O service (EI OS) or interrupt processing.
Page 130: Registers And Register Details
9.3 Registers and Register Details 9.3 Registers and Register Details Interrupt/DTP enable register Bit number Address : 000030 ENIR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Interrupt/DTP cause register Bit number Address : 000031 EIRR Read/write (R/W) (R/W) (R/W)
Page 131: Interrupt/Dtp Cause Register (Eirr: External Interrupt Request Register)
9.3 Registers and Register Details 9.3.2 Interrupt/DTP cause register (EIRR: External interrupt request register) Interrupt/DTP cause register Bit number Address : 000031 EIRR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value When read, EIRR indicates the current external interrupt/DTP requests. When written, EIRR clears the flip-flop values indicating those requests.
Page 132: Operations
9.4 Operations 9.4 Operations 9.4.1 External interrupts Once an external interrupt request is set, this resource issues an interrupt request signal to the interrupt controller when a request specified by the ELVR register is input to the corresponding pin. The interrupt controller identifies the priority levels of the simultaneous interrupts, and issues an interrupt request to the MC-16 CPU if the interrupt from this resource has the highest priority level.
Page 133: Dtp Operation
9.4 Operations 9.4.2 DTP operation To activate the intelligent I/O service, the user program initially sets the address of a register, assigned between 000000 and 0000FF , in the I/O address pointer of the intelligent I/O service descriptor. Then, the user program sets the start address of the memory buffer in the buffer address pointer. The DTP operation sequence is almost the same as for external interrupts.
Page 134: Switching Between External Interrupt And Dtp Requests
9.4 Operations 9.4.3 Switching between external interrupt and DTP requests To switch between external interrupt and DTP requests, use the ISE bit in the ICR register corresponding to this resource, which is in the interrupt controller. Each pin is individually assigned ICR. Thus, a pin is used for a DTP request if ’1’...
Page 135: Notes On Use
9.5 Notes on use 9.5 Notes on use 9.5.1 Conditions on the externally connected peripheral when DTP is used DTP supports only external peripherals that automatically clear a request once a transfer is completed. The system must be designed so that a transfer request is canceled within three machine cycles (provisional) after transfer operation starts.
Page 137: Chapter 10 Delayed Interrupt Generation Module
Chapter 10: Delayed Interrupt Generation Module 10.1 Outline The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI OS).
Page 138: Operations
10.4 Operations 10.4 Operations 10.4.1 Delayed interrupt occurrence When the CPU writes ’1’ to the relevant bit of DIRR by software, the request latch in the delayed interrupt source module is set and an interrupt request is issued to the interrupt controller. If this interrupt has the highest priority or if there is no other interrupt request, the interrupt controller issues an interrupt request to the F MC-16 CPU.
Page 139: Chapter 11 Communication Prescaler
Chapter 11: Communication Prescaler 11.1 Outline The operation clock for the UART is obtained by dividing the machine clock. UART is designed so that a constant baud rate can be obtained for a variety of machine clocks by the user of the communication prescaler.
Page 140: Register And Register Details
11.3 Register and Register Details 11.3 Register and Register Details 11.3.1 Clock Division Control Registers Clock Division Control Register 0, 1, 2, 3, 4 Address : 00002C Bit number 00002E CDCR0 000034 — — — DIV3 DIV2 DIV1 DIV0 CDCR1 000087 CDCR2 00008F...
Page 141: Operations
11.4 Operations 11.4 Operations Depending on the machine clock φ to be used, the communication prescaler register should be set as follows. For details please refer to Chapter 12, UART. φ φ machine clock DIV3 DIV2 DIV1 DIV0 /div 4 MHz 6 MHz 1 MHz 8 MHz...
Page 143: Chapter 12 Uart
Chapter 12: UART 12.1 Outline UART is a serial I/O port for asynchronous communications or CLK synchronous communications. UART has the following features: • Full-duplex double buffers • Asynchronous or CLK synchronous communications • Multi-processor mode • Built-in dedicated baud rate generator Asynchronous: 9615, 31250, 4808, 2404, 1202 bps (At an internal machine clock CLK synchronous: 1 M, 500 K, 250 K, 125 K, 62.5 Kbps...
Page 144: Block Diagram
12.2 Block Diagram 12.2 Block Diagram From Communication Reception Prescaler interrupt (to CPU) Baud rate SCK0/1/2/3/4 generator Transmission Transmission clock Clock interrupt Reception clock selection (to CPU) Upper part of PPG timer circuit (PPG1) Reception control Transmission control circuit circuit External clock Transmission Start bit detect...
Page 145: Register And Register Details
12.3 Register and Register Details 12.3 Register and Register Details Serial mode register Address : 000020 Bit number 000024 000028 SMR0 Reserved SCKE 000082 SMR1 000088 SMR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write SMR3 Initial value SMR4 Serial control register Address : 000021 Bit number...
Page 146: Serial Mode Register (Smr0/1/2/3/4)
12.3 Register and Register Details 12.3.1 Serial Mode Register (SMR0/1/2/3/4) Serial mode register Address : 000020 Bit number 000024 000028 SMR0 Reserved SCKE 000088 SMR1 000082 SMR2 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) SMR3 Initial value SMR4 The SMR register specifies the UART operation mode.
Page 147 12.3 Register and Register Details [bit 1] SCKE (SCLK enable): This bit is used to specify whether to use the SCK0 pin as a clock input pin or clock output pin in CLK synchronous mode (mode 2) communication. Set ’0’ in this bit in CLK asynchronous mode or external clock mode. The SCK0 pin is used as a clock input pin.
Page 148: Serial Control Register (Scr0/1/2/3/4)
12.3 Register and Register Details 12.3.2 Serial Control Register (SCR0/1/2/3/4) Serial control register Address : 000021 Bit number 000025 000029 SCR0 000083 SCR1 000089 SCR2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write SCR3 SCR4 Initial value The SCR register controls the transfer protocol for serial communications. [bit 15] PEN (Parity enable): This bit is used to specify whether to perform serial data communication using a parity bit.
Page 149 12.3 Register and Register Details [bit 11> A/D (Address/data): This bit is used to specify the data format of the frame to be sent or received in multi-processor asyn- chronous communication mode (mode 1). Data frame [initial value] Address frame [bit 10] REC (Receiver error clear): This bit is used to clear the SSR register error flags (PE, ORE, and FRE).
Page 150: Serial Input Data Register (Sidr0/1/2/3/4)/ Serial Ouput Data Register (Sodr0/1/2/3/4)
12.3 Register and Register Details 12.3.3 Serial Input Data Register (SIDR0/1/2/3/4)/ Serial Ouput Data Register (SODR0/1/2/3/4) Serial input register/Serial output register Address : 000022 Bit number 000026 00002A SIDR0/SODR0 000084 SIDR1/SODR1 00008A SIDR2/SODR2 SIDR3/SODR3 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Page 151 12.3 Register and Register Details [bit 13] FRE (Framing error) This interrupt request flag is set when a framing error occurs during reception. To clear a set flag, write ’0’ to the REC bit (bit 10) of the SCR register. When this bit is set, the data in SIDR is invalid.
Page 152: Operations
12.4 Operations 12.4 Operations 12.4.1 Operation modes Table 12.4.1a lists the operation modes of UART. The modes can be switched by setting a value in the SMR or SCR register. Table 12.4.1a UART operation modes Data Mode Parity Operation mode Stop bit length length Yes/No...
Page 153: Table 12.4.2B Baud Rates And Reload Values
12.4 Operations (2) Internal timer When ’110’ is set in CS2 to CS0 and an internal timer is selected, the 16-bit timer (timer 0) is used in reload mode. The baud rate is calculated as described below in this case: (∅÷N)/(16 ×...
Page 154: Asynchronous Mode
12.4 Operations 12.4.3 Asynchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.3a gives the data format. SIN0, SOT0 (Mode 0) Start LSB MSB Stop (Mode 1) A/D Stop 01001101 is transferred. Figure 12.4.3a Transfer data format (modes 0 and 1) As shown in Figure 12.4.3a, the transfer data always starts from the start bit (’L’...
Page 155: Clk Synchronous Mode
12.4 Operations 12.4.4 CLK synchronous mode (1) Transfer data format UART handles NRX (non return to zero) format data only. Figure 12.4.4a shows the transmission/reception clock and data. SODR write Mark SCLK RXE, TXE SIN0, SOT0 (Mode 2) 01001101 is transferred. Figure 12.4.4a Transfer data format (mode 2) When the internal clock (dedicated baud rate generator or internal timer) is selected, a data reception synchronization clock is automatically generated upon data transmission.
Page 156 12.4 Operations (3) Start of communication Communication is started by writing data in the SODR register. Virtual transmission data must be writ- ten to the SODR register even when only reception is to be performed. (4) End of communication The end of communication can be checked by ’1’ written to the RDRF flag of the SSR register. Use the ORE bit of the SSR register to check whether communication has been successful.
Page 157: Interrupt Occurrence And Flag Set Timing
12.4 Operations 12.4.5 Interrupt occurrence and flag set timing UART has five flags and two interrupt causes. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE indicates a parity error, ORE indicates an overrun error, and FRE indicates a framing error. These three flags are set when the corresponding error occurs during reception, and are cleared when ’0’...
Page 158: Figure 12.4.5C Timing To Set Ore And Rdrf (Mode 2)
12.4 Operations Then, an interrupt request is issued to the CPU. If the ORE flag is active, the data in SIDR is invalid. Data RDRF Reception interrupt Figure 12.4.5c Timing to set ORE and RDRF (mode 2) (4) Transmission in modes 0, 1, and 2 TDRE is cleared when a data item is written into the SODR register.
Page 159: I2Os (Intelligent I/O Service)
12.4 Operations 12.4.6 I OS (Intelligent I/O service) For I OS, see the section describing I 12.4.7 Notes on use To set a communication mode, ensure that UART is not in operation. The data sent or received during mode setting is not guaranteed. 12.4.8 Application Mode 1 is used when two or more slave CPUs are connected to a single host CPU (see Figure 12.4.8a).
Page 160: Figure 12.4.8B Flow Chart Of Communication In Mode 1
12.4 Operations (Host CPU) START Select transfer mode 1. Set the data for selecting the slave CPUs in D0 to D7 and set ’1’ in A/D to transfer one byte. Set ’0’ in A/D. Reception is enabled. Communication with the slave CPU End communication? Communicate with other slave CPU?
Page 161: Chapter 13 Ie Bus
Chapter 13: IE Bus 13.1 Outline IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. It is designed for use in automotive and general industrial applications. The communication protocol of the IEBus has the following features: •...
Page 162: Block Diagram
13.2 Block Diagram 13.2 Block Diagram Uuit Address Register Slave Address Register Multiaddress Control Bit Set Register Telegraph Length Set Register Write Data Buffer (8-byte FIFO) Master Address Read Register Multiaddress Control Bit Read Register Control Protocol Circuitry Controller Telegraph Length Set Register Lock Read Register Read Dta Buffer (8-byte FIFO) Command Register...
Page 163: Registers And Register Details
13.3 Registers and Register Details 13.3 Registers and Register Details Command register upper byte (CMRH) Bit Number Address: 000077 CMRH PCOM GOTM GOTS Reserved Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Command register lower byte (CMRL) Bit Number.
Page 164: Figure 13.3B Registers Of Ie Bus (2/3)
13.3 Registers and Register Details Mutliaddress, control bit set register (DCWR) Bit Number Address: 000075 DCWR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Telegraph length set register (DEWR) Bit Number Address: 000074 DECR Read/write (R/W) (R/W) (R/W) (R/W) (R/W)
Page 165: Figure 13.3C Registers Of Ie Bus (3/3)
13.3 Registers and Register Details Master address read register (MARH, MARL) Bit Number Address: 00007D Reserved Reserved Reserved MA11 MA10 MA09 MA08 MARH Reserved Read/write Initial value Bit Number Address: 00007C MA07 MA06 MA05 MA04 MA03 MA02 MA01 MA00 MARL Read/write Initial value Multiaddress, control bit read register (DCRR)
Page 166: Command Register Upper Byte (Cmrh)
13.3 Registers and Register Details 13.3.1 Command register upper byte (CMRH) Command register upper byte (CMRH) Bit Number Address: 000077 CMRH Reserved PCOM GOTM GOTS Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bits 15 and 14] MD1, MD0 (Mode select): These bits are used to select the IEBus operation mode.
Page 167: Table 13.3.1B Setting For Gotm And Gots
13.3 Registers and Register Details [bit 11] TIE (Transmit interrupt enable): This bit controls transmit interrupt as described below. Transmit interrupt disabled Transmit interrupt enabled The transmit interrupt is occurred under the following condition: • In master transmit, after master address field has been transmitted, the master unit has won in arbitration.
Page 168: Command Register Lower Byte (Cmrl)
13.3 Registers and Register Details 13.3.2 Command register lower byte (CMRL) Command register lower byte (CMRL) Bit Number. Address: 000076 RDBC WDBC CMRL TIT1 TIT0 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bit 7] RXS RX input pin polarity selected for external driver/receiver. Table 13.3.2a Interval for the occurrence of data transmit interrupt RX input status RX pin as postive logic input.
Page 169: Table 13.3.2D Internal Clock Frequency
13.3 Registers and Register Details [bit 3, 2] CS1, CS0 (Cycle select): These bits control both the CPU internal clock cycle and IEBUS controller clock cycle and CS1 and CS0 must be set to ‘0’. . Table 13.3.2d Internal clock frequency CPU internal clock φ...
Page 170: Unit Address Register (Mawh, Mawl)
13.3 Registers and Register Details 13.3.3 Unit address register (MAWH, MAWL) Unit address register (MAWH, MAWL) Bit Number Address: 000071 Reserved Reserved Reserved Reserved MA11 MA10 MA09 MA08 MAWH Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Bit Number Address: 000070 MA07...
Page 171: Mutliaddress, Control Bit Set Register (Dcwr)
13.3 Registers and Register Details 13.3.5 Mutliaddress, control bit set register (DCWR) Mutliaddress, control bit set register (DCWR) Bit Number Address: 000075 DCWR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value [bit 15, 14, 13, 12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication select bits): These bits are used to select multiaddress (more than one slave) or normal communication (one slave).
Page 172: Telegraph Length Set Register (Dewr)
13.3 Registers and Register Details 13.3.6 Telegraph length set register (DEWR) Telegraph length set register (DEWR) Bit Number Address: 000074 DECR Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value This register is used to set the number of data bytes to be transmitted and is valid only for data transmission.
Page 173: Status Register Upper Byte (Strh)
13.3 Registers and Register Details 13.3.7 Status register upper byte (STRH) Status register upper byte (STRH) Bit Number Address: 000079 STRH Read/write (R/W) (R/W) (R/W) Initial value [bit 15] COM (Communication status): This bit indicates the communication status as described below. Communication is prohibited Communication is enabled When this bit is ‘0’...
Page 174 13.3 Registers and Register Details [bit 11] RIF (Receive interrupt flag): This bit is set when receive interrupt is occurred. No receive interrupt request Have receive interrupt request This bit is cleared by writing ‘0’ to this bit or after the extended intelligent I/O service has been served. This bit is written ‘0’...
Page 175: Status Register Lower Byte (Strl)
13.3 Registers and Register Details 13.3.8 Status register lower byte (STRL) Status register lower byte (STRL) Bit Number Address: 000078 WDBF RDBF WDBE RDBE STRL Read/write Initial value [bit 7] WDBF (Write data buffer full): This flag indicates the status of the write data buffer (WDB). Write data buffer is not full Write data buffer is full This bit is set when WDB is full and cleared when at least one byte of data can be written into WDB.
Page 176: Table 13.3.8A Status Flag
13.3 Registers and Register Details [bit 3-0] ST3, ST2, ST1, ST0 (Operation status bits) These bits indicates the communication status of the unit and generates the corresponding interrupt during transmission or reception. By reading these bits, the communication status of the unit can be known.
Page 177: Lock Read Register (Lrrh, Lrrl)
13.3 Registers and Register Details 13.3.9 Lock read register (LRRH, LRRL) Lock read register (LRRH, LRRL) Bit Number Address: 00007B Reserved Reserved Reserved LD11 LD10 LD09 LD08 LRRH Read/write (R/W) Initial value Bit Number Address: 00007A LD07 LD06 LD05 LD04 LD03 LD02 LD01...
Page 178: Master Address Read Register (Marh, Marl)
13.3 Registers and Register Details 13.3.10 Master address read register (MARH, MARL) Master address read register (MARH, MARL) Bit Number Address: 00007D Reserved Reserved Reserved MA11 MA10 MA09 MA08 MARH Reserved Read/write Initial value Bit Number Address: 00007C MA07 MA06 MA05 MA04 MA03...
Page 179: Multiaddress, Control Bit Read Register (Dcrr)
13.3 Registers and Register Details 13.3.11 Multiaddress, control bit read register (DCRR) Multiaddress, control bit read register (DCRR) Bit Number Address: 00007F DCRR Read/write Initial value [bit 15-12] DO3, DO2, DO1, DO0 (Multiaddress/normal communication bits): In slave mode, the received multiaddress bit from the master is stored in bit DO0. If the unit itself is the master, the multiaddress/normal communication set bits (DO3-0) in multiaddress, control bit set register (DCWR) is read out.
Page 180: Telegraph Length Read Register (Derr)
13.3 Registers and Register Details 13.3.12 Telegraph length read register (DERR) Telegraph length read register (DERR) Bit Number Address: 00007E DERR Read/write Initial value if the unit itself is the receiver, this register stores the number of data specified by telegraph length field. If the unit itself is the transmitter, the telegraph length bits in telegraph length set register (DEWR) are read.
Page 181: Read Data Buffer (Rdb)
13.3 Registers and Register Details 13.3.13 Read data buffer (RDB) Read data buffer (RDB) Bit Number Address: 000081 Read/write Initial value This register (internally is a 8-byte FIFO buffer) stores received data in data field of the communication frame. When eight byte data have been received, RDB becomes full and receive interrupt is generated. Then data in RDB should be read out before the next coming byte of data is received as shown in Table 13.3.13a .
Page 182: Write Data Buffer (Wdb)
13.3 Registers and Register Details 13.3.14 Write data buffer (WDB) Write data buffer (WDB) Bit Number Address: 000080 Read/write Initial value This register (internally is a 8-byte FIFO buffer) stored data to be transmitted in data field of the communication frame. The data write interrupt timing is set by the two bits TIT1, TIT0 in command register (CMRL).
Page 183: Iebus Communication Protocol
13.4 IEBus Communication Protocol 13.4 IEBus Communication Protocol 13.4.1 Overview IEBus (Inter Equipment Bus) is a small-scale two-line serial bus interface intended to transfer data between equipment and equipment. • Communication method Data are transferred by means of half duplex asynchronous communication. •...
Page 184: Determining Bus Mastership (Arbitration)
13.4 IEBus Communication Protocol 13.4.2 Determining bus mastership (arbitration) The equipment connected to the IEBus performs an operation to occupy the bus when it controls another equipment. This operation is called arbitration. Arbitration is to grant the bus mastership to one of several units that have simultaneously started transmission.
Page 185: Communication Address
13.4 IEBus Communication Protocol 13.4.4 Communication address In IEBus, each equipment is assigned to a specific 12-bit communication address. The communication address is consisted of: Higher 4 bits:group number (identify which group the equipment belongs to) Lower 8 bits:unit number (identify each equipment in one group) 13.4.5 Multiaddress communication In normal communication mode, the communication is performed on a one-to-one basis, i.e.
Page 186: Transfer Protocol
13.4 IEBus Communication Protocol 13.4.6 Transfer protocol The signal transmit format of the IEBus is shown as below Master Telegraph Field Name Slave address Control field Data field Header address field length field field No. of bits 8 1 1 Master Slave Telegraph...
Page 187: Table 13.4.6A Number Of Transmit Data Bytes Setting
13.4 IEBus Communication Protocol (3) Slave address field This field outputs the address of the other unit with which the master is to communicate and is consisted of 12 bits of slave address with MSB transmitting first, parity bit and acknowledge bit. After a 12-bit slave address has been transmitted, a parity bit is output to ensure that the slave address is not received by mistake.
Page 188 13.4 IEBus Communication Protocol case, the second and following communication frames will transmit the remaining data bytes specified in the telegraph length field. The function of telegraph length field differs when the master is in transmit mode (bit 3 of control bits is ‘1’) or receive mode (bit 3 of control bits is ‘0’) as follow: •...
Page 189 13.4 IEBus Communication Protocol • At the end of data field The acknowledge bit is defined as: ‘0’: The transmit data is recognized (ACK) ‘1’: The transmit data is not recognized (NAK) The acknowledge bit is ignored in multiaddress communication. 1.
Page 190: Transmit Data
13.4 IEBus Communication Protocol 13.4.7 Transmit data The content in data field is controlled by the control bits in control field and is shown below: Table 13.4.7a Control bits setting Note Note 2 Bit 3 Function Bit 2 Bit 1 Bit 0 Slave status (SSR) read Undefined...
Page 191: Table 13.4.7C Meaning Of Slave Status
13.4 IEBus Communication Protocol (1) Slave status (SSR) read (control bits: 0H, 6H) By reading the slave status, the master can understand why the slave has not returned the acknowledge bit (ACK). The slave status is determined in respect to the result of the last communication performed by the slave unit.
Page 192 13.4 IEBus Communication Protocol (3) Read lock address (control bits: 4H, 5H) When the lock address is read (control bits: 4H, 5H), the address (12-bit) of the master that has issued the lock instruction is configured in 1-byte units as shown below and is read. Control bits: 4H Lower 8 bits Control bits: 5H...
Page 193: Bit Format
13.4 IEBus Communication Protocol 13.4.8 Bit format The format of the bits constituting an IEBus communication frame is shown below: Logic ‘1’ Logic ‘0’ Synchronizatio Data Pause Synchronizatio Data Preparation period period period period period period Logic ‘1’: voltage difference between inter-bus wires (BUS+ and BUS-)is below 20 mV (low level) Logic ‘0’: voltage difference between inter-bus wires (BUS+ and BUS-) is above 120 mV (high level) Preparation period: First low-level period (logic ‘1’) Synchronization period: Next high-level period (logic ‘0’)
Page 194: Operation
13.5 Operation 13.5 Operation 13.5.1 IEBus control (1) Master transmit The unit is set as master transmit to transmit data to the slave by sending data/command control bits as AH, BH, EH or FH. The sequences for operating in master transmit are described as below: 1.
Page 195: Table 13.5.1A Time Required To Write Transmit Data To Wdb After Transmit Interrupt Has Occurred
13.5 Operation 5. If error occurs during transmission or in multi-frame communication the number of data byte specified in DEWR cannot be transmitted completely, the state code (3H) indicating transmission terminated without all data transmitted is set in STRL:ST3-0. Transmit interrupt will occur. At this time, the content of communication error can be known by checking the status of TSL, PEF, TE in status register (STRH).
Page 196 13.5 Operation (4) Slave receive This mode is set when the slave unit receive control bits AH, BH, EH or FH from the master. The sequences for operating as slave receive are described as below: 1. After the slave returns the acknowledge bit in telegraph length field, the number of receive data byte is written in the telegraph length read register (DERR).
Page 197: Communication Status
13.5 Operation 13.5.2 Communication status In the status register, there are four bits ST3-0 indicating the status code. After the status code has been set, interrupt request is generated. During the interrupt routine, the communication status can be investigated by reading the status register. But at the beginning of master, slave and multiaddress receive, no interrupt will be generated (1) Master, slave data transmit (transmit interrupt occurs) When the unit won the arbitration in multiaddress or master address field, it becomes master unit.
Page 198: Table 13.5.2C Meaning Of Status Code St3-0 For Slave Receive
13.5 Operation (3) Slave receive (receive interrupt occurs) When data/command is received from the master unit, the status code ST3-0 is set and shown as below: Table 13.5.2c Meaning of status code ST3-0 for slave receive Code Name Code ST3-0 Content Indicates that the slave unit has received the telegraph field correctly from Slave receive...
Page 199: Program Flow Example For Iebus Controller
13.5 Operation 13.5.3 Program flow example for IEBus controller (1) Main routine Begin IEBus initial setup Enable IEBus controller IEBus controller operates (2) Interrupt routine This routine is executed when start of transmission or end of reception. In interrupt routine, the status code (ST3-0) in status register STRL is read, then the transmit data can be written or receive data can be read.
Page 200 13.5 Operation (3) IEBus initial setup The initial setup sequence includes setting its unit address, the command register and releasing the communication inhibit state. If the unit is not set as master, there is no need to set the slave address in slave address register.
Page 201 13.5 Operation (4) Master transmit routine After the communication inhibit state is released, the unit won the arbitration and acts as master. Then master transmit routine is used to transmit data to the slave. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as master transmit has been set.
Page 202 13.5 Operation (5) Slave transmit routine After the slave receives the control bits and is set as slave transmit, this routine is used to transmit data to the master. This routine is executed inside interrupt routine with ST3-0 bits (upper 2 bits are 00) in status register indicating the status as slave transmit has been set.
Page 203 13.5 Operation (6) Master receive routine After the master transmit the control bits, this routine is used for the master to receive data, slave address or log address from the slave. This routine is consisted of four parts depending on the content of ST3-0. 1.
Page 204 13.5 Operation 3. Master receive ends normally (ST3-0 is 6H) Begin Note1 Read out multiaddress, control bits Read multiaddress, control bits and telegraph length bits and master receive byte number Done by hardware number of master receive data byte RDB read Read out master receive data N - 1 Done by hardware...
Page 205 13.5 Operation 4. Master reception ends without all data being received (ST3-0 is 7H) Begin Note1 Read out multiaddress, control bits Read multiaddress, control and master receive byte number bits and telegraph length bits Done by hardware number of master receive data byte STRH/L read Note2 RDBE = 1?
Page 206: Timing Diagram Of Multiple Frame Transmission
13.5 Operation 13.5.4 Timing Diagram of Multiple Frame Transmission 1. When setting ‘1’ on WDBC (Master side of master transmission) Frist Frame Second Frame DataN-3(04H) DataN-2(03H) Start Multi-Add Master- Add Slave-Add Control Telegraph bytes DataN-1(FFH) DataN(FEH) Can read the rest of the transmission byte Transmission data left is 0 DERR Read...
Page 207: Figure 13.5.4B When Setting '0' On Wdbc (Master Side Of Master Transmission)
13.5 Operation 2. When setting ‘0’ on WDBC (Master side of master transmission) Frist Frame Second Frame DataN-3(04H) Master- Add Slave-Add DataN-2(03H) Start Multi-Add Control Telegraph bytes DataN-1(02H) DataN(01H) Can read the rest of the transmission bytes Transmission data left is 0 DERR Read DEER...
Page 208: Timing Diaram Of Transmission Data When An Error Is Generated
13.5 Operation 13.5.5 Timing diaram of transmission data when an error is generated 1. The following is an example when the master transmission, an error is generated at the second byte data on the slave side. NAK is received by the master. the following data is transmitted at the second frame.
Page 209: Figure 13.5.5B Error Happened On The Master Side When Master Transmission
13.5 Operation 2. The following is an example when the master transmission, an error is generated at the second byte data on the master side. The following data is transmitted at the second frame. Slave reception movements until the figure becomes the maximum transmission byte Header Data Filed...
Page 211: Chapter 14 8/16-Bit Ppg
Chapter 14: 8/16-Bit PPG 14.1 Outline The 8/16-bit PPG timer is an 8-bit reload timer module, and outputs PPG by control pulse output according to timer operation. The hardware includes two eight-bit down counters, four eight-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs.
Page 212: Block Diagram
14.2 Block Diagram 14.2 Block Diagram PPG0 output enable PPG0 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division A/D converter Peripheral clock 2-division Peripheral clock PPG0 Output latch Invert Clear PEN0 PCNT Count clock (down counter) selection Reload Time base counter output ch1-borrow 512-division of main clock L/H selection...
Page 213: Figure 14.2B 8-Bit Ppg Ch1 Block Diagram
14.2 Block Diagram PPG0 output enable PPG1 Peripheral clock 16-division Peripheral clock 8-division Peripheral clock 4-division UART Peripheral clock 2-division Peripheral clock PPG1 Output latch Invert Clear Count clock PEN1 selection ch0 borrow PCNT (down counter) Time base counter output Reload 512-division of main clock L/H selection...
Page 214: Registers And Register Details
14.3 Registers and Register Details 14.3 Registers and Register Details PPG0 operation mode control register Bit No. Address: ch0 000044H PEN0 PE00 PIE0 PUF0 Reserved PPGC0 (R/W) (R/W) (R/W) (R/W) Read/write Initial value PPG1 operation mode control register Bit No. PEN1 PE10 PIE1 PUF1 MD1 MD0 Address: ch0 000045H...
Page 215: Ppg0 Operation Mode Control Register (Ppgc0)
14.3 Registers and Register Details 14.3.1 PPG0 operation mode control register (PPGC0) PPG0 operation mode control register Bit No. Address: ch0 000044H PEN0 PE00 PIE0 PUF0 Reserved PPGC0 Read/write (R/W) (R/W) (R/W) (R/W) Initial value PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
Page 216 14.3 Registers and Register Details This bit controls the PPG counter underflow as described below. PUF0 Operation PPG counter underflow is not detected [initial value] PPG counter underflow is detected In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’ is written to this bit when an underflow occurs as a result of the ch0 counter value becoming between 00H and FFH.
Page 217: Ppg1 Operation Mode Control Register (Ppgc1)
14.3 Registers and Register Details 14.3.2 PPG1 operation mode control register (PPGC1) PPG1 operation mode control register Bit No. Address: ch0 000045H PEN1 PE10 PIE1 PUF1 MD1 MD0 Reserved PPGC1 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value PPGC0 is a seven-bit control register that selects the operation mode of the block, controls pin outputs, selects count clock, and controls triggers.
Page 218 14.3 Registers and Register Details [bit 11] PUF1 (PPG underflow flag): PPG counter underflow bit This bit controls the PPG counter underflow as described below. PUF1 Operation PPG counter underflow is not detected [initial value] PPG counter underflow is detected In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, ’1’...
Page 219: Ppg0, 1 Output Pin Control Register (Ppgoe)
14.3 Registers and Register Details 14.3.3 PPG0, 1 output pin control register (PPGOE) PPG0,1 output control register Bit No. Reserved Reserved PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 PPGOE Address: ch0 1 0046H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value This is an 8-bit control register that controls the pin output of this block.
Page 220: Reload Register (Prll/Prlh )
14.3 Registers and Register Details 14.3.4 Reload register (PRLL/PRLH ) Reload register H Bit No. Address: ch0 000041H PRLH ch1 000043H Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value Reload register L Bit No. Address: ch0 000040H PRLL ch1 000042H Read/write...
Page 221: Operations
14.4 Operations 14.4 Operations This block has two channels of 8-bit PPG units. These two channels can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit PPG mode, and single-channel 16-bit PPG mode. Each of the 8-bit PPG units has two eight-bit reload registers. One reload register is for the L side (PRLL) and the other is for the H side (PRLH).
Page 222: Figure 14.4A Ppg Output Operation, Output Waveform
14.4 Operations (2) PPG output operation In this block, the ch0 PPG is activated to start counting when ’1’ is written to bit 7 (PEN0) of the PPGC0 (PWM operation mode control) register. Similarly, the ch1 PPG is activated to start counting when ’1’ is written to bit 15 (PEN1) of the PPGC1 register.
Page 223: Figure 14.4B 8+8 Ppg Output Operation Waveform
14.4 Operations (4) Count clock selection The count clock used for the operation of this block is supplied from a peripheral clock or time base counter. The count clock can be selected from six types. Select ch0 clock at bit 4 to 2 (PCM2 to 0) of the PPGOE register, and ch1 clock at bit 7 to S (PCS2 to 0) of the PPGOE register.
Page 224 14.4 Operations (6) Interrupts For this module, an interrupt becomes active when the reload value is counted out and a borrow occurs. In 8-bit PPG 2ch mode or 8-bit prescaler + 8-bit PPG mode, an interrupt is requested by a borrow in each counter.
Page 225: Figure 14.4C Write Timing Chart
14.4 Operations (8) Reload register write timing In a mode other than 16-bit PPG mode, it is recommended to use a word transfer instruction to write data in reload registers PRLL and PRLH. If two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing.
Page 227: Chapter 15 16-Bit Reload Timer (With Event Count Function)
Chapter 15: 16-Bit Reload Timer (with Event Count Function) 15.1 Outline The 16-bit reload timer 1 consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TIN) and one output pin (TOUT), and a control register. It has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down detecting a given edge of the pulse input to the external bus pin, and either of the two functions can be selectively used.
Page 228: Block Diagram
15.2 Block Diagram 15.2 Block Diagram 16-bit reload register Reload RELD OUTE 16-bit down-counter OUTL INTE GATE CTL. CSL1 Clock selector CNTE Clear CSL0 OSCLR Re-trigger IN CTL Port (TIN) EXCK Output enable φ φ φ Prescaler Port (TOUT) clear MOD2 MOD1 Serial baud rate (ch0)
Page 229: Registers And Register Details
15.3 Registers and Register Details 15.3 Registers and Register Details Timer control status register (upper) Bit number  Address: ch0 000049  TMCSR0-2 ch1 00004D — — — — CSL1 CSL0 MOD2 MOD1  (HIGH) ch2 000051 Read/write — — —...
Page 230: Timer Control Status Register (Tmcsr)
15.3 Registers and Register Details 15.3.1 Timer control status register (TMCSR) Timer control status register (upper) Bit number  Address: ch0 000049  TMCSR0-2 ch1 00004D — — — — CSL1 CSL0 MOD2 MOD1  (HIGH) ch2 000051 Read/write — —...
Page 231 15.3 Registers and Register Details [Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits set the operation mode and I/O pin functions. The MOD2 bit selects the I/O functions. When MOD2 = “0”, the input pin functions as a trigger input. In this case, the reload register contents is loaded to the counter when an active edge is input to the input pin and count operation proceeds.
Page 232 15.3 Registers and Register Details [Bit 4] RELD (Reload) This bit enables reload operations. When RELD is “1”, the timer operates in reload mode. In this mode, the timer loads the reload register contents into the counter and continues counting whenever an underflow occurs (when the counter value changes from 0000 to FFFF ).
Page 233: Tmr (16-Bit Timer Register)/Tmrlr (16-Bit Reload Register)
15.3 Registers and Register Details 15.3.2 TMR (16-bit timer register)/TMRLR (16-bit reload register) 16-bit timer register (upper)/ 16-bit reload register (upper) Bit number  Address: ch0 00003B Address: ch0 00004B  ch1 00003F TMR0-2/ ch1 00004F  TMRLR0-2 ch2 000053 (HIGH) (R/W) (R/W)
Page 234: Operation
15.4 Operation 15.4 Operation 15.4.1 Internal clock operation The machine clock divided by 2 , or 2 can be selected as the clock sources for operating the timer from an internal divide clock. The external input pin can be selected as either a trigger input or gate input by a register setting.
Page 235: Underflow Operation
15.4 Operation 15.4.2 Underflow operation An underflow is defined for this timer as the time when the counter value changes from 0000 to FFFF Therefore, an underflow occurs after (reload register setting + 1) counts. If the RELD bit in the control register is “1” when the underflow occurs, the contents of the reload register is loaded into the counter and counting continues.
Page 236: Input Pin Functions (For Internal Clock Mode)
15.4 Operation 15.4.3 Input pin functions (for internal clock mode) The TIN pin can be used as either a trigger input or a gate input when an internal clock is selected as the clock source. When used as a trigger input, input of an active edge causes the timer to load the reload register contents to the counter and then start count operation after clearing the internal prescaler.
Page 237: Output Pin Functions
15.4 Operation 15.4.5 Output pin functions In reload mode, the TOUT pin performs toggle output (inverts at each underflow). In one-shot mode, the TOUT pin functions as a pulse output that outputs a particular level while the count is in progress. The OUTL bit of the control register sets the output polarity.
Page 238: Counter Operation State
15.4.7 Counter operation state The counter state is determined by the CNTE bit in the control register and the internal WAIT signal. Avail- able states are: CNTE = “0” and WAIT = “1” (STOP state), CNTE = “1” and WAIT = “1” (WAIT state for trig- ger), and CNTE = “1”...
Page 239: Chapter 16 A/D Converter
Chapter 16: A/D Converter 16.1 Outline The A/D converter converts analog input voltages into digital values. The A/D converter has the following features: Conversion time: 5.2 µs min. per channel (at 16 MHz machine clock) • • RC sequential compare conversion format with sample and hold circuit •...
Page 240: Block Diagram
16.2 Block Diagram 16.2 Block Diagram AVCC AVSS D/A converter Sequential compare register Comparator Sample and hold circuit Data register ADCR1, 2 A/D control register 1 A/D control register 2 ADCS1, 2 Activation by trigger ADTG Activation by timer Operation clock PPG01 output Prescaler Figure 16.2a Block Diagram of A/D converter...
Page 241: Registers And Register Details
16.3 Registers and Register Details 16.3 Registers and Register Details Control Status Registers (Upper Byte) Bit number Address : 000037 BUSY INTE PAUS STS1 STS0 STRT ADCS2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value Control Status Registers (Lower Byte) Bit number Address : 000036 ANS2...
Page 242: Control Status Registers (Adcs1 And Adcs2)
16.3 Registers and Register Details 16.3.1 Control status registers (ADCS1 and ADCS2) These registers are used to control the A/D converter and display the status. Control Status Registers (Upper Byte) Bit number Address : 000037 BUSY INTE PAUS STS1 STS0 STRT ADCS2 (R/W) (R/W)
Page 243 16.3 Registers and Register Details [bit 12] PAUS (A/D conversion pause): This bit is set when the A/D conversion is paused. Only one register is available for storing the A/D conversion result. Therefore, unless the conversion results are transferred by I2OS, the result data would be continuously updated and destroyed in contin- uous conversion.
Page 244 16.3 Registers and Register Details [bits 7 and 6] MD1 and MD0 (A/D converter mode set): These bits are used to set the A/D converter operation mode. Operation mode Single mode. Reactivation during operation is allowed. Single mode. Reactivation during operation is not allowed. Continuous mode.
Page 245 16.3 Registers and Register Details [bits 2, 1, and 0] ANE2, ANE1, and ANE0 (Analog end channel set): Use these bits to set the A/D conversion end channel. ANE2 ANE1 ANE0 End channel * When the same channel is written to ANE2 to ANE0 and ANS2 to ANS0, conversion is performed for one channel only (single conversion).
Page 246: Adcr1 And Adcr0 (Data Registers)
16.3 Registers and Register Details 16.3.2 ADCR1 and ADCR0 (Data registers) Data Registers (Upper Byte) Bit number Address : 000039 Reserved ADCR2 Read/write Initial value Data Registers (Lower Byte) Bit number Address : 000038 ADCR1 Read/write Initial value Figure 16.3.2a Data Registers [bit 15] This is reserved bit.
Page 247 16.3 Registers and Register Details [bit 12, 11] : CT1, CT0 (Compare Time) These bits is used for setting the comparsion time in terms of machine cycle. Comparsion time machine cycle Comparsion time 176 machine cycle 22ms at 8MHz machine clock 22ms at 16MHz machine 352 machine cycle clock...
Page 248: Operations
16.4 Operations 16.4 Operations The A/D converter operates in the sequential compare format, and has a 8-bit resolution. Since the A/D converter has only one register (8 bits) for storing the conversion result, the conversion data registers (ADCR0) are updated each time conversion is completed. Thus, the A/D converter must not be used alone for continuous conversion.
Page 249: Figure 16.4A Flow Chart Of A/D Conversion
16.4 Operations (3) Stop mode In this mode, the converter sequentially converts the analog inputs specified with the ANS and ANE bits, pausing each time conversion for one channel is completed. To release pausing, activate the A/D converter again. After the conversion is completed for the end channel specified with the ANE bits, conversion is repeated from the analog inputs of the ANS.
Page 250 16.4 Operations Usage Starting I OS in single mode •To terminate conversion after analog inputs AN1 to AN3 are converted •To transfer conversion data sequentially to addresses 200H to 206H •To start conversion by software •To use the highest interrupt level OS setting ICR3 #08H...
Page 251 16.4 Operations Usage Starting I OS in continuous mode •To convert analog inputs AN3 to AN5 and obtain two conversion data items for each channel •To transfer conversion data sequentially to addresses 600H to 60CH • •To start conversion by external edge input To use the highest interrupt level OS setting ICR3...
Page 252 16.4 Operations Usage Starting I OS in stop mode •To convert analog input AN3 12 times at fixed intervals •To transfer conversion data sequentially to addresses 600H to 618H • •To start conversion by external edge input To use the highest interrupt level OS setting ICR3 #08H...
Page 253: Figure 16.4B Flow Chart Of Data Protection Function
16.4 Operations (5) Conversion data protection The A/D converter has a conversion data protection function that enables continuous conversion and preservation of multiple data items using I Since there is only one conversion data register, its value is updated each time conversion is com- pleted.
Page 254: Notes On Use
16.5 Notes on use 16.5 Notes on use To start the A/D converter upon an external trigger or internal timer, A/D activation factor bits STS1 and STS0 of the ADCS2 register are used. Ensure that the input values of the external trigger or internal timer are inactive.
Page 255: Chapter 17 D/A Converter
Chapter 17: D/A Converter 17.1 Outline This is an R-2R format D/A converter, having an eight-bit resolution. The D/A converter has two channels. Output control can be performed independently for the two channels using the D/A control register.
Page 256: Block Diagram
17.2 Block Diagram 17.2 Block Diagram MC-16LX BUS DA07 DA17 DA06 DA16 DA05 DA15 DA01 DA11 DA10 DA00 DAE0 DAE1 Standby control Standby control DA output ch1 DA output ch0 Figure 17.2a Block Diagram of D/A Cobverter Chapter 17: D/A Converter MB90580 Series...
Page 257: Registers And Register Details
17.3 Registers and Register Details 17.3 Registers and Register Details D/A converter data register 1 Bit number Address : 00003B DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DAT1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value D/A converter data register 0 Bit number Address : 00003A...
Page 258: Dat0/1 ( D/A Data Register)
17.3 Registers and Register Details 17.3.1 DAT0/1 ( D/A data register) D/A converter data register 1 Bit number Address : 00003B DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 DAT1 Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value D/A converter data register 0 Bit number Address : 00003A...
Page 259: Operations
17.4 Operations 17.4 Operations D/A output is started by writing a desired D/A output value to the D/A data register (DADR) and setting ’1’ to the enable bit for the corresponding D/A output channel in the D/A control register (DACR). Disabling D/A output turns off the analog switch that is inserted serially into the output of each D/A con- verter channel.
Page 261: Chapter 18 Pulse Width Counter (Pwc) Timer
Chapter 18: Pulse Width Counter (PWC) Timer 18.1 Outline This module is a multi-function 16-bit up-counter with a reload function and a function for counting pulse widths on the input signal. The module hardware consists of a 16-bit up-counter, input pulse divider, divide ratio control register, four count input pins, one pulse output pin, and a 16-bit control register.
Page 262: Block Diagram
18.2 Block Diagram 18.2 Block Diagram PWCR read Error detection Internal clock PWCR (machine clock/4) Reload Data transfer Overflow Clock 16-bit up-count timer Clock divider Timer clear CKS1 Count enable Divider clear Control circuit CKS0 Start edge End edge Divider selection selection ON/OFF...
Page 263: Regiaters And Register Details
18.3 Regiaters and Register Details 18.3 Regiaters and Register Details PWC Control Status Register (Upper Byte) Bit number Address : 000055 PWCSR STRT STOP EDIR EDIE OVIR OVIE POUT (HIGH) Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value PWC Control Status Register (Lower Byte) Bit number Address : 000054 CSK1...
Page 264: Pwc Control Status Register (Pwcsr)
18.3 Regiaters and Register Details 18.3.1 PWC control status register (PWCSR) PWC Control Status Register (Upper Byte) Bit number Address : 000055 PWCSR STRT STOP EDIR EDIE OVIR OVIE POUT (HIGH) Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value PWC Control Status Register (Lower Byte) Bit number Address : 000054...
Page 265 18.3 Regiaters and Register Details [bit 13] EDIR (End interrupt request) This flag indicates when counting ends in pulse width count mode. A count end interrupt request is generated if the interrupt is enabled (bit 12: EDIE = "1") when this bit is set. Set timing Set when pulse width counting ends (when the count result is placed in PWCR).
Page 266 18.3 Regiaters and Register Details [bit 9] ERR (Error) This flag is used when continuous counting is performed in pulse width count mode. The flag indicates that the next count has completed before the previous count result has been read from PWCR.
Page 267 18.3 Regiaters and Register Details [bits 5, 4] PIS1, PIS0 (Pulse input select) These bits select the input pin on which to perform pulse width counting. PIS1 PIS0 Count Input Pin Selection Always set this value. (Initial value) Setting unavailable (Do not set any of these values.) After a reset: Initialized to "00 ".
Page 268 18.3 Regiaters and Register Details [bits 2, 1, 0] MOD2, MOD1, MOD0 (MOD2, 1, 0) These bits select the operation mode and the pulse edges for width counting. MOD2 MOD1 MOD0 Operation Mode/Count Edge Selection Timer mode, no pulse output (Initial value) Timer mode, pulse output enabled (using the POT pin): Reload mode only Inter-edge pulse width count mode ( ⇑...
Page 269: Pwc Data Buffer Register (Pwcr)
18.3 Regiaters and Register Details 18.3.2 PWC data buffer register (PWCR) PWC Data Buffer Register (Upper Byte) Bit number Address : 000057 PWCR (HIGH) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write Initial value PWC Data Buffer Register (Lower Byte) Bit number Address : 000056 PWCR...
Page 270: Divide Ratio Control Register (Divr)
18.3 Regiaters and Register Details 18.3.3 Divide Ratio Control Register (DIVR) Divide Ratio Control Register Bit number Address : 000058 — — — — — — DIV1 DIV0 DIVR Read/write (R/W) (R/W) Initial value This register is only used in divided period count mode (bits 2, 1, 0: MOD2, 1, 0 of PWCSR = "011"). In divided period count mode, pulses input from the count pin are divided by the divide ratio set in this register and the period of the divided signal is measured.
Page 271: Pwc Noise Cancelling Register (Rncr)
18.3 Regiaters and Register Details 18.3.4 PWC noise cancelling register (RNCR) PWC Noise Cancelling register Bit number Address : 000086 — — — — — RNCR Read/write (R/W) (R/W) (R/W) Initial value The PWC noise removal circuit is used for removing noises form the input signal. H level and L level detection will be applied to the input signal after it was ‘cleaned’...
Page 272: Operations
18.4 Operations 18.4 Operations (1) Summary of Operation This block is a multi-function timer based on a 16-bit up-count timer and incorporating a count input pin and 8-bit input divider. The block has two main functions: a timer function and a pulse width count function.
Page 273: Figure 18.4C Pulse Width Count Operation (Single-Shot Count Mode, "H" Width Count Mode)
18.4 Operations (2) Pulse Width Count Function This function counts the time period between specified events on an input pulse. After the function is activated, the count does not start until the specified count start edge is input. The counter is cleared to "0000 "...
Page 274: Table 18.4A Count Clock Selection
18.4 Operations (3) Count Clock Selection The timer count clock can be selected from three internal clock sources. The available clock sources are listed below. Table 18.4a Count Clock Selection PWCSR/bit7, 6:CKS1, 0 Selected Internal Count Clock Machine cycle divided by 4 (0.25µs for a 16MHz machine cycle) (Initial value) Machine cycle divided by 16 (1.0µs for a 16MHz machine cycle)
Page 275: Figure 18.4E Operation Mode Selection
18.4 Operations (4) Operation Mode Selection The operation mode and count mode are selected by PWCSR settings. • Operation mode setting PWCSR bits 2, 1, and 0: Bits MOD2, MOD1, and MOD0 (Selects timer or pulse width count mode and specifies which edges control counting.) •...
Page 276: Table 18.4B Start And Stop Bit Functions
18.4 Operations (5) Starting and Stopping the Timer and Pulse Width Count Starting, restarting, and forcibly halting each operation is performed using bits 15 and 14 (STRT and STOP) of PWCSR. Writing "0" to the STRT bit starts or restarts operation and writing "0" to the STOP bit forcibly halts operation.
Page 277 18.4 Operations (6) Clearing the Timer The 16-bit up-count timer is cleared to 0000 in the following cases. • A reset • When counting starts after detection of a count start edge in pulse width count mode(6) (7) Details of Timer Mode Operation (a) Single-Shot Operation Mode When the timer is started in this mode, the timer counts up on each count clock.
Page 278: Table 18.4D Count Clock And Period
18.4 Operations (e) Timer Period If the timer is started in single-shot mode after setting 0000 to PWCR, the timer overflows after 65536 counts and the count stops. The following formula calculates the time from the timer starting to the timer stopping.
Page 279: Figure 18.4F Flowchart Of Timer Mode Operation
18.4 Operations (g) Timer Operation Flowchart Count clock selection Operation and count mode selection Clear interrupt flag Settings Enable interrupt Set pulse output initial value Set value to PWCR Start by STRT bit Restart Reload operation mode Single-shot operation mode Reload PWCR value in timer Start count Start count...
Page 280: Table 18.4E Count Input Pin Selection (N = 3 To 0)
18.4 Operations (8) Details of Pulse Width Count Mode Operation (a) Count Input Pins and Pin Selection The pins used to input the signal for pulse width counting are fixed as pin PWC0 for ch0, PWC1 for ch1, PWC2 for ch2, and PWC3 for ch3. Always set bits 4 and 5 of PWCSR to "00" on the MB90580. Table 18.4e Count Input Pin Selection (n = 3 to 0) PIS1 PIS0...
Page 281: Table 18.4F Count Modes
18.4 Operations (d) Count Mode and Count Operation The count mode can be selected from five different modes. The mode determines which part of the input pulse to measure. To accurately measure the width of high frequency pulses, a mode is available to divide the input pulses by a specified ratio and to measure the resulting period.
Page 282 18.4 Operations Table 18.4f Count Modes (Continued) Count Operation Count Mode MOD2 MOD1 MOD0 (w: Pulse width being measured) Inter-edge pulse width count ⇑ ⇓ Count start Count stop ⇓ ⇑ Start Stop ⇑ ⇓ Start Stop Measures the width between consecutive input edges. •...
Page 283: Table 18.4G Pulse Width Count Range
18.4 Operations (f) Pulse Width/Period Calculation Calculate the width or period of the measured pulse from the count result read from PWCR after the count ends as follows.  … Measured pulse width or period (µs)   n … Count result stored in PWCR ...
Page 284: Figure 18.4G Flowchart Of Operation In Pulse Width Count Mode
18.4 Operations (i) Flowchart of the Pulse Width Count Operation Count clock selection Operation and count mode selection Clear interrupt flag Settings Enable interrupt Set pulse output initial value Start by STRT bit Restart Continuous count mode Single-shot count mode Count start edge detected Count start edge detected Clear timer...
Page 285: Precautions
18.5 Precautions 18.5 Precautions (1) Changing Register Values Changing the values of the following PWCSR bits when the timer is operating is prohibited. Only change bit values before starting the timer or after operation stops. [bits 7, 6] CKS1, CKS0: Clock selection bits [bits 5, 4] PIS1, PIS0: Count input pin selection bits [bit 3] S/C: Count mode (single-shot or continuous) selection bit [bits 2, 1, 0] MOD2, MOD1, MOD0: Operating mode and count edge selection bits...
Page 286 18.5 Precautions (8) Divided Period Count Mode Note that the input pulses are divided when divided period count mode is used in pulse width count mode and therefore the pulse width calculated from the count result is an average value. (9) Restarting the Timer During Operation Depending on the timing, the following may occur when the timer is restarted after starting the count operation.
Page 287: Chapter 19 Clock Monitor Function
Chapter 19: Clock Monitor Function 19.1 Outline Clock Monitor Function is used to output the machine clock to a port pin. This clock output is generated by dividing the machineclock by 2 to 2 19.2 Block Diagram CKEN machine clock FRQ2 Clock division FRQ1...
Page 288: Registers And Register Details
19.3 Registers and Register Details 19.3 Registers and Register Details Clock Output Enable Register Bit number Address : 00003E — — — — CKEN FRQ2 FRQ1 FRQ0 CLKR (R/W) (R/W) (R/W) (R/W) Read/write Initial value Figure 19.3a Registers of Clock Monitor Function 19.3.1 Clock output enable register (CLKR) Bit number Address : 00003E...
Page 289: Chapter 20 16-Bit I/O Timer
Chapter 20: 16-Bit I/O Timer 20.1 Outline The 16-bit I/O timer consists of a 16-bit free-run timer, two output compare modules, and four input capture modules. The count values of this timer are used as the base timer for output compare and input capture. Using this function, two independent waveforms can be output based on 16-bit free-run timer to enable measurement of input pulse withs and external clock cycles.
Page 290 20.1 Outline Input capture (×4) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free-run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin.
Page 291: Block Diagram
20.2 Block Diagram 20.2 Block Diagram 20.2.1 Overall Block Diagram of 16-bit I/O Timer Control logic Interrupt 16-bit free-run timer 16-bit timer Clear Output compare 0 Compare register 0 OUT0 Output compare 1 OUT1 Compare register 1 Input capture 0 Capture register 0 Edge selection Input capture 1...
Page 292: Block Diagram Of 16-Bit Free-Run Timer
20.2 Block Diagram 20.2.2 Block Diagram of 16-bit free-run timer Interrupt request IVFE STOP MODE CLR CLK1 CLK0 Divider Comparator 0 16-bit up counter Clock Count value output Figure 20.2.2a Block diagram of 16-bit free-run timer 20.2.3 Block Diagram of Output Comparison 16-bit timer counter value (T15 to T00) OUT0 OTE0...
Page 293: Block Diagram Of Input Capture
20.2 Block Diagram 20.2.4 Block Diagram of Input Capture IN0 (IN2) Edge detection Capture data register 0 EG11 EG10 EG01 EG00 16-bit timer counter value (T15 to T00) IN1 (IN3) Capture data register 1 Edge detection ICP1 ICP0 ICE1 ICE0 Interrupt 1 (3) Interrupt 0 (2) Figure 20.2.4a Block diagram of Input Capture...
Page 294: Registers And Register Details
20.3 Registers and Register Details 20.3 Registers and Register Details 20.3.1 16-bit free-run timer 16-bit Timer Data Register (Upper) Bit Number TCDTH Address: 00006D Read/write Initial value 16-bit Timer Data Register (Lower) Bit Number TCDTL Address: 00006C Read/write Initial value 16-bit Timer Control Status Register Bit Number Reserved...
Page 295 20.3 Registers and Register Details 20.3.1.1 16-bit free-run timer data register 16-bit Timer Data Register (Upper) Bit Number TCDTH Address: 00006D Read/write Initial value 16-bit Timer Data Register (Lower) Bit Number TCDTL Address: 00006C Read/write Initial value The data register can read the count value of the 16-bit free-run timer. The counter value is cleared to ’0000’...
Page 296 20.3 Registers and Register Details 20.3.1.2 16-bit free-run timer control status register 16-bit Timer Control Status Register Bit Number Reserved IVFE STOP MODE CLK1 CLK0 TCCS Address: 00006E Read/write Initial value [bit 7] Reserved bit Always write ’0’ to this bit. [bit 6] IVF This bit is an interrupt request flag of the 16-bit free-run timer.
Page 297 20.3 Registers and Register Details [bit 3] MODE The MODE bit is used to set the initialization condition of the 16-bit free-run timer. When ’0’ is set, the counter value can be initialized by a reset or a clear bit (bit 2: CLR). When ’1’...
Page 298: Output Comparison
20.3 Registers and Register Details 20.3.2 Output comparison The output compare module consists of 16-bit compare registers, compare output pins, and control regis- ter. If the value written to the compare register of this module matches the 16-bit free-run timer value, the output level of the pin can be reversed and an interrupt can be issued.
Page 299 20.3 Registers and Register Details 20.3.2.1 Compare register Output Compare Register 0, 1 Bit Number Address: 00005B OCCP0 (Upper) OCCP1 (Upper) 00005D Read/write Initial value Bit Number Address: 00005A OCCP0 (Lower) 00005C OCCP1 (Lower) Read/write Initial value This 16-bit compare register is compared with the 16-bit free-run timer. Since the initial register value is undefined, set a value before enabling the register.
Page 300 20.3 Registers and Register Details 20.3.2.2 Control status register Output Compare Control Status Register 0, 1 Bit Number Address: 00005F OCS1 CMOD OTE1 OTE0 OTD1 OTD0 Read/write Initial value Bit Number OCS0 Address: 00005E ICP1 ICP0 ICE1 ICE0 CST1 CST0 Read/write Initial value [bits 15, 14, and 13] Unused bits...
Page 301 20.3 Registers and Register Details [bits 7 and 6] ICP1 and ICP0 These bits are used as output compare interrupt flags. ’1’ is written to these bits when the compare reg- ister value matches the 16-bit free-run timer value. While the interrupt request bits (ICE1 and ICE0) are enabled, an output compare interrupt occurs when the ICP1 and ICP0 bits are set.
Page 302: Input Capture
20.3 Registers and Register Details 20.3.3 Input capture This module detects a rising or falling edge or both edges of an externally input signal and stores the 16-bit free-run timer value in a register. In addition, this module can generate an interrupt upon detection of an edge.
Page 303 20.3 Registers and Register Details 20.3.3.1 Input capture data register Input Capture Data Register 0, 1, 2, 3 Address: 000061 Bit Number 000063 000065 IPCP0 (Upper) CP15 CP14 CP13 CP12 CP12 CP11 CP09 CP08 000067 IPCP1 (Upper) IPCP2 (Upper) Read/write IPCP3 (Upper) Initial value Address: 000060...
Page 304 20.3 Registers and Register Details 20.3.3.2 Control status register Input Capture Control Status Register ch0,1 & Ch2,3 Bit Number Address: 000068 ICS01 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 00006A ICS23 Read/write Initial value [bits 7 and 6] ICP1 and ICP0 These bits are used as input capture interrupt flags.
Page 305: Operations
20.4 Operations 20.4 Operations 20.4.1 16-bit free-run timer The 16-bit free-run timer starts counting from counter value ’0000’ after the reset is released. The counter value is used as the reference time for the 16-bit output compare and 16-bit input capture operations. The counter value is cleared in the following conditions: •...
Page 306: 16-Bit Output Compare
20.4 Operations 20.4.2 16-bit output compare In 16-bit output compare operation, an interrupt request flag can be set and the output level can be reversed when the specified compare register value matches the 16-bit free-run timer value. Sample output waveform when compare registers 0 and 1 are used (The initial output value is 0.) Counter value FFFF BFFF...
Page 307: 16-Bit Input Capture
20.4 Operations 20.4.3 16-bit input capture In 16-bit input capture operation, an interrupt can be generated upon detection of a specified valid edge, fetching the 16-bit free-run timer value and writing it to the capture register. Sample input capture fetch timing Capture 0: Rising edge Capture 1: Falling edge Capture example: Both edges...
Page 308: Timing
20.5 Timing 20.5 Timing 20.5.1 16-bit free-run timer count timing The 16-bit free-run timer is incremented based on the input clock (internal or external clock). When exter- nal clock is selected, the 16-bit free-run timer is incremented at the rising edge. Free-run timer count timing External clock input...
Page 309: Output Compare Timing
20.5 Timing 20.5.2 Output compare timing In output compare operation, a compare match signal is generated when the free-run timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued. The output reverse timing upon a compare match is synchronized with the counter count timing. Compare operation upon update of compare register When the compare register is updated, comparison with the counter value is not performed.
Page 310: Input Capture Input Timing
20.5 Timing 20.5.3 Input capture input timing Capture timing for input signals Counter value Input capture Valid edge input Capture signal Capture register Interrupt Chapter 20: 16-Bit I/O Timer MB90580 Series...
Page 311: Chapter 21 Rom Correction Module
Chapter 21: ROM Correction Module 21.1 Outline When the setting of the address is the same as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved.
Page 312: Registers And Register Details
21.3 Registers and Register Details 21.3 Registers and Register Details Program Address Detect Register 0/1 byte byte byte access initial value undefined PADR0 1FF2H/1FF1H/1FF0H undefined PADR1 1FF5H/1FF4H/1FF3H Program Address Detect Control Status Register Bit number Address : 009E — — —...
Page 313: Program Address Detect Control Status Register (Pacsr)
21.3 Registers and Register Details 21.3.2 Program Address detect Control Status Register (PACSR) Program Address Detect Control Status Register Bit number Address : 009E — — — — — — AD1E AD0E PACSR Read/write (–) (–) (–) (–) (R/W) (–) (R/W) (–) Initial value...
Page 314: Operations
21.4 Operations 21.4 Operations When the program counter indicates the same address as the ROM Correction Address register, the INT9 instruction will be executed. By processing the INT9 interrupt service routine, the ROM correction function can be achieved. There are two address registers, in each containing a compare enable bit. When the address register and the program counter are in agreement, and when the compare enable bit is at ‘...
Page 315: Application Example
21.5 Application Example 21.5 Application Example (1) System Structure EPROM F2MC16-LX pull up resistor connector (UART) Figure 21.5a System Structure Example (2) EPROM memory map address:content 0000H:number of bytes of the corrected program No. 0 (0 implies no ROM correction) 0001H:bit 7-0 program address No.
Page 316: Figure 21.5B Rom Correction Processing Example
21.5 Application Example (6) INT9 interrupt In the interrupt routine, the address that produces the interrupt can be known by checking the stack program couter value. The information stacked during interrupt will be discarded. MB90580 FFFFFFh Erroneous Program External E PROM O Number of program byte Register setting...
Page 317: Figure 21.5C Rom Correction Processing Flow Diagram
21.5 Application Example Reset Read the 00h of E PROM INT9 0000h (E2PROM)=0 Read the Address 0001h~0003h (E2PROM) PADR0 (MCU) To Corrected Program JMP 000400h Read the Corrected Program 0010h~0090h (E2PROM) Corrected Program Execution 000400h~000480h 000400h~000480h (MCU) End of Corrected Program Enable compare JMP FF0050h MOV PACSR, #02h...
Page 319: Chapter 22 Rom Mirroring Module
Chapter 22: ROM Mirroring Module 22.1 Outline In ROM Mirroring Module the FF bank of the ROM can be seen through the 00 bank when chosen during register setting. 22.2 Block Diagram ROM Mirrroring Register Address Area FF bank 00 bank Figure 22.2a Block Diagram of ROM Mirroring Module...
Page 320: Registers And Register Details
22.3 Registers and Register Details 22.3 Registers and Register Details ROM Mirror Function Select Register Bit number Address : 0006F — — — — — — — ROMM Read/write (–) (–) (–) (–) (–) (–) (–) Initial value (–) (–) (–) (–) (–)
Page 321: Figure 22.3B Memory In Single Chip Mode
22.3 Registers and Register Details ADDRESS FFFFFF ROM Area ROM Area Address 1 010000 ROM Area 004000 002000 Address 2 RAM Area RAM Area 000100 0000C0 Internal IO Area IO Area Area 000000 When MI= ‘ 1’ When MI= ‘ 0’ Figure 22.3b Memory in Single Chip Mode ADDRESS FFFFFF...
Page 323: Appendix A I/O Map
Appendix A: I/O Map I/O Map Table A.1a lists the addresses assigned to the registers of each microcontroller resource Table A.1a I/O map Address Register Abbreviation Access Resource Initial value Port 0 data register PDR0 Port 0 XXXXXXXX Port 1 data register PDR1 Port 1 XXXXXXXX...
Page 324 A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value Clock division control register 0 CDCR0 Communication prescaler 0 0---1111 Reserved area Clock division control register 1 CDCR1 Communication prescaler 1 0---1111 Reserved area Interrupt /DTP enable register ENIR 00000000 Interrupt/DTP cause register...
Page 325 A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value XXXXXXXX Output Compare Register 0 OCCP0 XXXXXXXX XXXXXXXX Output Compare Output Compare Register 1 OCCP1 (Channel 0 To 1) XXXXXXXX Output Compare Control Status Register 0 OCS0 0000--00 Output Compare Control Status Register 1...
Page 326 A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value Serial mode register 4 SMR4 00000000 Serial control register 4 SCR4 00000100 UART4 Serial input register/serial output register 4 SIDR/ XXXXXXXX SODR4 Serial status register 4 SSR4 00001-00 Port 0 resistor register...
Page 327 A.1 I/O Map Table A.1a I/O map (Continued) Address Register Abbreviation Access Resource Initial value 1FF0 Program address detection register 0 XXXXXXXX 1FF1 Program address detection register 1 PADR0 XXXXXXXX 1FF02 Program address detection register 2 XXXXXXXX Program patch manipulation 1FF3 Program address detection register 3 XXXXXXXX...
Page 329: Appendix B Instructions
APPENDIX B: Instructions B.1 Addressing In the F MC-16LX, the address format is determined by either the instruction’s effective address specification, or by the instruction code itself (implied addressing). B.1.1 Effective address field The address formats specified in the effective address field are shown in Table B.1.1a. Table B.1.1a Effective Address Field Code Notation...
Page 330: Addressing Details
B.1 Addressing B.1.2 Addressing Details (1) Immediate value (#imm) This format specifies the operand value directly. • #imm4 • #imm8 • #imm16 • #imm32 (2) Compressed direct address (dir) In this format, the operand specifies the low-order 8 bits of the memory address. Bits 8 to 15 of the address are specified by the DPR.
Page 331 B.1 Addressing (5) Register indirect (@RWj j = 0 to 3) This format accesses the memory address indicated by the contents of the general-purpose register RWj. When RW0/RW1 is used, bits 16 to 23 of the address are indicated by DTB; if RW3 is used, bits 16 to 23 of the address are indicated by SPB, and if RW2 is used, bits 16 to 23 of the address are indicated by ADB.
Page 332: Fig. B.1.2A Register List Configuration
B.1 Addressing (10) Accumulator indirect (@A) This format has two types: one in which the contents of AL specify bits 00 to 15 of the address and DTB indicates bits 16 to 23; and one in which the low-order 24 bits of A specify bits 00 to 23 of the address. (11) I/O direct (io) In this format, the memory address of the operand is specified directly by the 8-bit displacement value.
Page 333 B.1 Addressing (17) Program counter relative branching address (rel) With this format, the address of the destination of a branching instruction is the sum of the value of the PC and the 8-bit displacement value. If the result exceeds 16 bits, the amount of the overflow is ignored and the bank register is not incremented or decremented;...
Page 334: Instruction Set
B.2 Instruction Set B.2 Instruction Set Table B.2a Explanation of Items in Table of Instructions Item Explanation Upper-case letters and symbols: ..Described as they appear in assembler. Mnemonic Lower-case letters: ......Replaced when described in assembler. Numbers after lower-case letters: ..Indicate the bit width within the instruction. Indicates the number of bytes.
Page 335 B.2 Instruction Set • Number of execution cycles The number of cycles required for the execution of an instruction is obtained by summing the value shown in the table for the “number of cycles” for the instruction in question, the compensation value (which depends on certain conditions), and the “number of cycles”...
Page 336: Table B.2B Explanation Of Symbols In Table Of Instructions
B.2 Instruction Set Table B.2b Explanation of Symbols in Table of Instructions Symbol Explanation 32-bit accumulator The bit length varies according to the instruction. Byte:.... Low-order 8 bits of AL Word: ..16 bits of AL Long: ... 32 bits of AL:AH High-order 16 bits of A Low-order 16 bits of A Stack pointer (USP or SSP)
Page 337: Table B.2C Effective Address Fields
B.2 Instruction Set Table B.2c Effective Address Fields Number of bytes in Code Notation Address format address extension [Note] (RL0) Register direct (RL1) “ea” corresponds to byte, word, and long- – word types, starting from the left (RL2) (RL3) @RW0 @RW1 Register indirect @RW2...
Page 338: Table B.2D Number Of Execution Cycles For Each Form Of Addressing
B.2 Instruction Set Table B.2d Number of Execution Cycles for Each Form of Addressing Number of accesses for Number of execution Code Operand each form of addressing cycles for each form of addressing Listed in Table of Listed in Table of Instructions Instructions @RWj...
Page 339: Table B.2F Compensation Values For Number Of Cycles Used To Calculate Number Of Program Fetch Cycles
B.2 Instruction Set Table B.2f Compensation Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory – External data bus (16 bits) – External data bus (8 bits) – Note: When the external data bus is used, it is necessary to add in the number of weighted cycles used for ready input and automatic ready.
Page 340: F 2 Mc-16Lx Instruction Set (351 Instructions)
B.2 Instruction Set B.2.1 F MC-16LX Instruction Set (351 Instructions) Table B.2.1a Transfer Instructions (Byte) (41 Instructions) Mnemonic Operation byte (A) ← (dir) ∗ ∗ ∗ A,dir byte (A) ← (addr16) ∗ ∗ ∗ A,addr16 byte (A) ← (Ri) ∗ ∗...
Page 341: Table B.2.1B Transfer Instructions (Word/Long-Word) (38 Instructions)
B.2 Instruction Set Table B.2.1b Transfer Instructions (Word/Long-Word) (38 Instructions) Mnemonic Operation word (A) ← (dir) ∗ ∗ ∗ MOVW A,dir word (A) ← (addr16) ∗ ∗ ∗ MOVW A,addr16 word (A) ← (SP) ∗ ∗ ∗ MOVW A,SP word (A) ← (RWi) ∗...
Page 342: Table B.2.1C Addition And Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions)
B.2 Instruction Set Table B.2.1c Addition and Subtraction Instructions (Byte/Word/Long-Word) (42 Instructions) Mnemonic Operation byte (A) ← (A) + imm8 ∗ ∗ ∗ ∗ A,#imm8 byte (A) ← (A) + (dir) ∗ ∗ ∗ ∗ A,dir byte (A) ← (A) + (ear) ∗...
Page 343: Table B.2.1D Increment And Decrement Instructions (Byte/Word/Long-Word) (12 Instructions)
B.2 Instruction Set Table B.2.1d Increment and Decrement Instructions (Byte/Word/Long-Word) (12 Instructions) Mnemonic Operation byte (ear) ← (ear) + 1 ∗ ∗ ∗ byte (eam) ← (eam) + 1 ∗ ∗ ∗ 5+(a) 2×(b) byte (ear) ← (ear) - 1 ∗...
Page 344: Table B.2.1F Unsigned Multiplication And Division Instructions (Word/Long-Word) (11 Instructions)
B.2 Instruction Set Table B.2.1f Unsigned Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) Mnemonic Operation ∗ ∗ DIVU word (AH) / byte (AL) Quotient → byte (AL) Remainder → byte (AH) ∗ ∗ DIVU A,ear word (A) / byte (ear) Quotient →...
Page 345: Table B.2.1G Signed Multiplication And Division Instructions (Word/Long-Word) (11 Instructions)
B.2 Instruction Set Table B.2.1g Signed Multiplication and Division Instructions (Word/Long-Word) (11 Instructions) Mnemonic Operation ∗ ∗ word (AH) / byte (AL) Quotient → byte (AL) Remainder → byte (AH) ∗ ∗ A,ear word (A) / byte (ear) Quotient → byte (A) Remainder →...
Page 346: Table B.2.1H Logical 1 Instructions (Byte/Word) (39 Instructions)
B.2 Instruction Set Table B.2.1h Logical 1 Instructions (Byte/Word) (39 Instructions) Mnemonic Operation byte (A) ← (A) and imm8 ∗ ∗ A,#imm8 byte (A) ← (A) and (ear) ∗ ∗ A,ear byte (A) ← (A) and (eam) ∗ ∗ A,eam 4+(a) byte (ear) ←...
Page 347: Table B.2.1I Logical 2 Instructions (Long-Word) (6 Instructions)
B.2 Instruction Set Table B.2.1i Logical 2 Instructions (Long-Word) (6 Instructions) Mnemonic Operation long (A) ← (A) and (ear) ∗ ∗ ANDL A,ear long (A) ← (A) and (eam) ∗ ∗ ANDL A,eam 7+(a) long (A) ← (A) or (ear) ∗...
Page 348: Table B.2.1L Shift Instructions (Byte/Word/Long-Word) (18 Instructions)
B.2 Instruction Set Table B.2.1l Shift Instructions (Byte/Word/Long-Word) (18 Instructions) Mnemonic Operation LH AH byte (A) ← Right rotate with carry ∗ ∗ ∗ RORC byte (A) ← Left rotate with carry ∗ ∗ ∗ ROLC byte (ear) ← Right rotate with carry ∗...
Page 349: Table B.2.1M Branch 1 Instructions (31 Instructions)
B.2 Instruction Set Table B.2.1m Branch 1 Instructions (31 Instructions) Mnemonic Operation LH AH BZ / BEQ rel Branch when (Z) = 1 BNZ / BNE rel Branch when (Z) = 0 BC / BLO rel Branch when (C) = 1 BNC / BHS rel Branch when (C) = 0 Branch when (N) = 1...
Page 350: Table B.2.1N Branch 2 Instructions (19 Instructions)
B.2 Instruction Set Table B.2.1n Branch 2 Instructions (19 Instructions) Mnemonic Operation LH AH Branch when byte (A) ≠ imm8 ∗ ∗ ∗ ∗ CBNE A,#imm8,rel ∗ ∗ ∗ ∗ CWBNE A,#imm16,rel Branch when word (A)≠ imm16 ∗ ∗ ∗ ∗...
Page 351: Table B.2.1O Other Control Instructions (Byte/Word/Long-Word) (36 Instructions)
B.2 Instruction Set Table B.2.1o Other Control Instructions (Byte/Word/Long-Word) (36 Instructions) Mnemonic Operation LH AH word (SP) ← (SP) -2, ((SP)) ← (A) PUSHW word (SP) ← (SP) -2, ((SP)) ← (AH) PUSHW word (SP) ← (SP) -2, ((SP)) ← (PS) PUSHW (SP) ←...
Page 352: Table B.2.1P Bit Manipulation Instructions (22 Instructions)
B.2 Instruction Set Table B.2.1p Bit Manipulation Instructions (22 Instructions) Mnemonic Operation LH AH I S T byte (A) ← ( dir:bp )b ∗ ∗ ∗ MOVB A,dir:bp byte (A) ← ( addr16:bp )b ∗ ∗ ∗ MOVB A,addr16:bp byte (A) ← ( io:bp )b ∗...
Page 353: Table B.2.1Q Accumulator Manipulation Instructions (Byte/Word) (6 Instructions)
B.2 Instruction Set Table B.2.1q Accumulator Manipulation Instructions (Byte/Word) (6 Instructions) Mnemonic Operation LH AH byte (A)0-7 ←→ (A)8-15 SWAP word (AH) ←→ (AL) ∗ SWAPW / XCHW A,T ∗ ∗ byte signed extension ∗ ∗ EXTW word signed extension ∗...
Page 354: Instruction Map
B.3 Instruction Map B.3 Instruction Map Because the F MC-16LX operation codes each consist of one or two bytes, the instruction map consists of numerous pages. The structure of the instruction map is shown below. First byte Basic Page Map Bit manipulation Character string “ea”...
Page 355: Fig. B.3B Correspondence Between Actual Instructions And The Instruction Maps
B.3 Instruction Map The correspondence between the actual instruction code and the instruction map is shown below. May not exist for some instructions Length differs according to the instruction Instruction code • • • First byte Second byte operand operand [Basic page map] [Extension page map] Note Note: Extended page maps are provided for bit manipulation instructions, character string manipulation...
Page 356: Table B.3.1A Basic
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 357: Table B.3.1B Bit Manipulation Instruction Map (First Byte = 6 Ch)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 358: Table B.3.1C Character String Manipulation Instruction Map (First Byte = 6Eh)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 359: Table B.3.1D Two-Byte Instruction Map (First Byte = 6Fh)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 360: Table B.3.1E "Ea" Instructions 1 (First Byte = 70H)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 361: Table B.3.1F "Ea" Instructions 22 (First Byte = 71H)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 362: Table B.3.1G "Ea" Instructions 3 (First Byte = 72H)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 363: Table B.3.1H "Ea" Instructions 4 (First Byte = 73H)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 364: Table B.3.1I "Ea" Instructions 5 (First Byte = 74H)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 365: Table B.3.1J "Ea" Instructions 6 (First Byte = 75H)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 366: Table B.3.1K "Ea" Instructions 7 (First Byte = 76H)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 367: Table B.3.1L "Ea" Instructions 8 (First Byte = 77H)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 368: Table B.3.1M "Ea" Instructions 9 (First Byte = 78H)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 369: Table B.3.1N Movea Rwi, Ea (First Byte = 79H)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 370: Table B.3.1O Mov Ri, Ea (First Byte = 7Ah)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 371: Table B.3.1P Movw Rwi, Ea (First Byte = 7Bh)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 372: Table B.3.1Q Mov Ea, Ri (First Byte = 7Ch)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 373: Table B.3.1R Movw Ea, Rwi (First Byte = 7Dh)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 374: Table B.3.1S Ch Ri, Ea (First Byte = 7Eh)
B.3 Instruction Map APPENDIX B: Instructions MB90580 Series...
Page 375: Table B.3.1T Xchw Rwi, Ea (First Byte = 7Fh)
B.3 Instruction Map MB90580 Series APPENDIX B: Instructions...
Page 377: Appendix C The Flash Memory In The Mb90F583
Appendix C: The Flash Memory in the MB90F583 C.1 Outline There is a 1M-bit Flash memory (128K word x 8/64K word x 16) located at the FE~FF bank of the CPU memory map in MB90F583. With the flash memory interface circuit, it is possible for read access from and program access to the CPU.
Page 378: Sector Structure Of 1M Bit Flash Memory
C.2 Sector Structure of 1M Bit Flash Memory C.2 Sector Structure of 1M Bit Flash Memory Sector structure of 1M bit flash memory in MB90F583 is shown in Figure C.2a. The address in the Figure C.2a shows upper and lower address of each sector. When accessing from CPU, SA0 is set in the FE bank register and SA1~4 are set in the FF Bank register.
Page 379: Flash Control Register (Fmcs)
C.3 Flash Control Register (FMCS) C.3 Flash Control Register (FMCS) Flash control register (FMCS) is a register which is used during programming or erasing the flash memory. Flash Control Register (FMCS) Bit Number Address: 0000AE LPM1 INTE RDYINT Reserved Reserved LPM0 FMCS Read/write...
Page 380: Figure C.3A Timing Of Rdyint And Rdy
C.3 Flash Control Register (FMCS) [bit 4] RDY (ReaDY) This bit is used to indicate whether the flash memory is ready for programming/erasing. When this bit is set to “0”, programming or erasing the flash memory is not allowed. However, it is possible to issue read/reset command and sector erase suspend command when this bit is “0”.
Page 381: Automatic Algorithm Initiation Method
C.4 Automatic Algorithm Initiation Method C.4 Automatic Algorithm Initiation Method To start the Automatic Algorithm in the flash memory, there are five types of commands, 2 types of read/reset, programming, chip erase and sector erase. For sector erase, there are the sector erase suspend and the sector erase resume command.
Page 382: Automatic Algorithm Execution Status
C.5 Execution Status of Automatic Algorithm In the flash memory, the programming or erasing can be done by Automatic Algorithm, so that there is a Hardware Sequence Flag in the flash memory, which indicates the operation status and the operation completion.
Page 383: Data Polling Flag (Dq7)
C.5 Execution Status of Automatic Algorithm C.5.1 Data polling flag (DQ7) Data polling flag is used to indicate whether the Automatic Algorithm is executing or completed by using data polling function. Table C.5.1a shows the status change of the data polling flag. •...
Page 384: Toggle Bit Flag (Dq6)
C.5 Execution Status of Automatic Algorithm C.5.2 Toggle bit flag (DQ6) Toggle bit flag is used to indicate whether the Automatic Algorithm is in progress or is completed by using toggle bit function. Table C.5.2a shows status change of the toggle bit flag. •...
Page 385: Exceeded Timing Limits Flag (Dq5)
C.5 Execution Status of Automatic Algorithm C.5.3 Exceeded timing limits flag (DQ5) Exceeded timing limits flag is used to indicate whether Automatic Algorithm has executed beyond the time (internal pulse count) specified in the flash memory. Table C.5.3a shows status change of the exceeded timing limits flag.
Page 386: Sector Erase Timer Flag (Dq3)
C.5 Execution Status of Automatic Algorithm C.5.4 Sector erase timer flag (DQ3) Sector erase timer flag is used to indicate whether the Automatic Algorithm is executed beyond the sector erase wait time after the sector erase command is issued. Table C.5.4a shows status change of the sector erase timer flag.
Page 387: Notes On Flash Memory Program/Erase
C.6 Details of Flash Memory Programming/Erasing C.6 Details of Flash Memory Programming/Erasing This section describes the following: command generated for initiating Automatic Algorithm, read/reset of flash memory, programming, chip erase, sector erase suspend and sector erase resume. Flash memory can execute Automatic Algorithm when repeating the bus write cycle in read/reset, pro- gramming, chip erase, sector erase, sector erase suspend and sector erase resume command sequence.
Page 388: Data Programming
C.6 Details of Flash Memory Programming/Erasing C.6.2 Data Programming This section will describe how to issue the programming command to program the flash memory. To initiate Automatic Program Algorithm in the flash memory, the programming command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and it needs to be sent continuously to the target sector in the flash memory.
Page 389: Figure C.6.2A Example Flowchart Of Progamming The Flash Memory
C.6 Details of Flash Memory Programming/Erasing Start Enable Flash memory write FMCS:WE (bit 5) Write command sequence ← (1) FxAAAA XXAA ← (2) Fx5555 XX55 ← (3) FxAAAA XXA0 ← (4) Write addr Write data Next address Internal address read Data Data polling (DQ7) Data...
Page 390: Chip Erase
C.6 Details of Flash Memory Programming/Erasing C.6.3 Chip Erase This section will describe how to issue the chip erase command to erase the whole chip. To erase all data from the flash memory, the chip erase command found in command sequence table (refer to Section C.4, Automatic Algorithm Initiation Method, Table C.4a) can be used and needs to be send continuously to the target address in the flash memory.
Page 391: Figure C.6.4A Example Flowchart Of Erasing Flash Memory
C.6 Details of Flash Memory Programming/Erasing Start Enable Flash memory erase FMCS:WE (bit 5) Erase command sequence ← (1) FxAAAA XXAA ← (2) Fx5555 XX55 ← (3) FxAAAA XX80 ← (4) Fx5554 XX55 ← (5) sector addr Erase code (30H) Sector erase time (DQ3) (6) Input code to erase sector (30H) Internal address read...
Page 392: Suspend Sector Erase
C.6 Details of Flash Memory Programming/Erasing C.6.5 Suspend Sector Erase This section will describe how to issue the sector erase suspend command to suspend sector erase operation in the flash memory. During sector erase, it is possible to read data from the sector which is not being erased.
Page 394 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9806 © FUJITSU LIMITED Printed in Japan...
Page 395 Known bugs in HM MB90580 1. Chapter 20.4.5 Output Compare Unit ===================================== The documentation refers to outputs OUT0/1 and OUT2/3. There does not exist OUT2 and OUT3 (see pinning). So compare register 0 corresponds to OUT0 only and compare register 1 to OUT1. last updated : 05-03-98...

This manual is also suitable for:

F2mc-16lx mb90v580 F2mc-16lx mb90583 F2mc-16lx mb90f583

Fujitsu F2MC-16LX MB90580 Series Hardware Manual

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21 Chapter 1 Overview

24 Chapter 1 Overview

35 Chapter 2 CPU

45 Chapter 2 CPU

51 Chapter 3 Memory

55 Chapter 3 Memory

67 Chapter 4 Clock and Reset

71 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

72 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

81 Chapter 6 Low Power Control Circuit

83 Chapter 6 Low Power Control Circuit

96 Chapter 7 Interrupt

101 Chapter 7 Interrupt

121 Chapter 8 Parallel Ports

129 Chapter 9 Dtp/External Interrupt

137 Chapter 10 Delayed Interrupt Generation Module

139 Chapter 11 Communication Prescaler

143 Chapter 12 UART

161 Chapter 13 IE Bus

21 Chapter 1 Overview

24 Chapter 1 Overview

35 Chapter 2 CPU

45 Chapter 2 CPU

51 Chapter 3 Memory

55 Chapter 3 Memory

67 Chapter 4 Clock and Reset

71 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

72 Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

81 Chapter 6 Low Power Control Circuit

83 Chapter 6 Low Power Control Circuit

96 Chapter 7 Interrupt

101 Chapter 7 Interrupt

121 Chapter 8 Parallel Ports

129 Chapter 9 Dtp/External Interrupt

137 Chapter 10 Delayed Interrupt Generation Module

139 Chapter 11 Communication Prescaler

143 Chapter 12 UART

161 Chapter 13 IE Bus

Also See for Fujitsu F2MC-16LX MB90580 Series

Related Manuals for Fujitsu F2MC-16LX MB90580 Series

Summary of Contents for Fujitsu F2MC-16LX MB90580 Series

21
Chapter 1 Overview

24
Chapter 1 Overview

35
Chapter 2 CPU

45
Chapter 2 CPU

51
Chapter 3 Memory

55
Chapter 3 Memory

67
Chapter 4 Clock and Reset

71
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

72
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

81
Chapter 6 Low Power Control Circuit

83
Chapter 6 Low Power Control Circuit

96
Chapter 7 Interrupt

101
Chapter 7 Interrupt

121
Chapter 8 Parallel Ports

129
Chapter 9 Dtp/External Interrupt

137
Chapter 10 Delayed Interrupt Generation Module

139
Chapter 11 Communication Prescaler

143
Chapter 12 UART

161
Chapter 13 IE Bus

21
Chapter 1 Overview

24
Chapter 1 Overview

35
Chapter 2 CPU

45
Chapter 2 CPU

51
Chapter 3 Memory

55
Chapter 3 Memory

67
Chapter 4 Clock and Reset

71
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

72
Chapter 5 Watchdog Timer, Timebase Timer, and Watch Timer Functions

81
Chapter 6 Low Power Control Circuit

83
Chapter 6 Low Power Control Circuit

96
Chapter 7 Interrupt

101
Chapter 7 Interrupt

121
Chapter 8 Parallel Ports

129
Chapter 9 Dtp/External Interrupt

137
Chapter 10 Delayed Interrupt Generation Module

139
Chapter 11 Communication Prescaler

143
Chapter 12 UART

161
Chapter 13 IE Bus