Supplement On External Pin And Internal Operation Timing - Fujitsu FR60 Hardware Manual

CHAPTER 16 DMA CONTROLLER (DMAC)
16.3.19 Supplement on External Pin and Internal Operation
Timing
This section provides supplementary information about external pins and internal
operation timing.
■ Minimum Effective Pulse Width of the DREQ Pin Input.
(The MB91F353A/351A/352A/353A do not have 0, 1, and 2 channels.)
Operation in all transfer modes (i.e., burst, step, block, and demand transfer) requires a minimum effective
pulse width of five system clock cycles (five cycles of external bus clock [CLKT]).
Note:
DACK output does not indicate acceptance of DREQ input. DREQ input is always accepted if DMA
is enabled but transfer has not started. Therefore, it is not necessary to retain DREQ input until
DACK output is asserted (except in demand transfer mode).
■ Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped
●
For 2-cycle transfer
For a demand transfer, be sure to set an address in an external area for the transfer source, the transfer
destination, or both.
• For transfer between external circuits:
When accessing the transfer source for the last DMA transfer, negate DREQ while the external WR pin
output is at the "L" level.
If DREQ is negated after the period when DACK and WR are at the "L" level, the next transfer may be
executed.
• For transfer between external and internal circuits:
When accessing the transfer source for the last DMA transfer, negate DREQ while the external RD pin
output is at the "L" level
If DREQ is negated after the period when DACK and RD are at the "L" level, the next transfer may be
executed.
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