Start/Stop Timing And Input/Output Timing Of Shift Operation - Fujitsu MB90480 Series Hardware Manual

18.5.3 Start/Stop Timing and Input/Output Timing of Shift
Operation
Start/stop timing and input/output timing of the shift operation are described below.
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Start/Stop timing and input/output timing of shift operation

• Start
Set the STOP bit and STRT bit of SMCS to "0" and "1", respectively.
• Stop
Operation is stopped by the end of data transfer or as soon as STOP = 1.
- If operation stopped because of STOP = 1: Stop is performed while SIR is "0", regardless
of the MODE bit.
- For an operation stop because of the end of data transfer: SIR is set to "1" and data
transfer is stopped regardless of the MODE bit.
Irrespective of the MODE bit, the BUSY bit becomes "1" in the serial data transfer state and "0"
during the stop state or R/W wait state. Read this bit for checking the data transfer state.
Timing charts illustrating the transfer operation in various modes are provided below. D07 to
D00 in the diagram represent output data.
❍ Internal shift clock mode (LSB First)
Figure 18.5-3 Start/stop timing in shift operation (using the internal clock)
SCK1, SCK2
STRT
BUSY
SOT1,SOT2
❍ External shift clock mode (LSB first)
Figure 18.5-4 Start/stop timing in shift operation (using the external clock)
SCK1,SCK2
STRT
BUSY
SOT1,SOT2
(Transfer start)
When MODE=0
DO0
(Transfer start)
When MODE=0
DO0
CHAPTER 18 EXPANDED I/O SERIAL INTERFACE
Output of "1"
(Transfer end)
DO7 (Data hold)
(Transfer end)
DO7 (Data hold)
401