Transfer Sequence - Fujitsu FR60 Hardware Manual
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Also See for FR60:
- Hardware manual (636 pages) ,
- User manual (104 pages) ,
- User manual (1038 pages)
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16.3.3
Transfer Sequence
The transfer type and the transfer mode that determine, for example, the operation
sequence after DMA transfer has started can be set independently for each channel
(Settings for TYPE[1:0] and MOD[1:0] of DMACB).
■ Selection of the Transfer Sequence
The following sequence can be selected with a register setting:
•
Burst 2-cycle transfer
•
Demand 2-cycle transfer
Note: The MB91F353A/351A/352A/353A do not support demand 2-cycle transfer.
•
Block/step 2-cycle transfer
•
Burst fly-by transfer
Note: The MB91F353A/351A/352A/353A do not support burst fly-by transfer.
•
Demand fly-by transfer
Note: The MB91F353A/351A/352A/353A do not support demand fly-by transfer.
•
Block/step fly-by transfer
Note: The MB91F353A/351A/352A/353A do not support block/step fly-by transfer.
■ Burst 2-Cycle Transfer
In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed continuously
for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified using a transfer source/
transfer destination address.
A peripheral transfer request, software transfer request, or external pin (DREQ) edge input detection
request can be selected as the transfer source.
Table 16.3-1 lists the specifiable transfer addresses for burst 2-cycle transfer.
Table 16.3-1 Specifiable Transfer Addresses for Burst 2-Cycle Transfer
Transfer source addressing
All 32-bit areas specifiable
[Features of a burst transfer]
•
When one transfer request is received, transfer is performed continuously until the transfer count
register reaches 0. The transfer count is the transfer count x block size (BLK[3:0] of DMACA x
DTC[15:0] of DMACA).
•
Another request occurring during transfer is ignored.
•
If the reload function of the transfer count register is enabled, the next request is accepted after transfer
ends.
•
If a transfer request for another channel with a higher priority is received during transfer, the channel is
switched at the boundary of the block transfer unit. Processing resumes only after the transfer request
for the other channel is cleared.
Direction
Transfer destination addressing
→
All 32-bit areas specifiable
497
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