Bus Operation Stop Bit (Halt = 1) - Fujitsu MB90420/5 (A) Series Hardware Manual

F2mc-16lx family 16-bit microcontrollers
Table of Contents

Advertisement

MB90420/5 (A) SERIES F

23.6.2 Bus Operation Stop Bit (HALT = 1)

The bus operation stop bit sets or cancels stopping of bus operation, or indicates its status
n Conditions for setting bus operation stop (HALT=1)
There are three conditions for setting bus operation stop (HALT = 1):
• After hardware reset
• When node status changed to bus off
• By writing 1 to HALT
Notes: • The bus operation should be stopped by writing 1 to HALT before the F
low-power consumption mode (stop mode, clock mode, and hardware stand-by mode).
If transmission is in progress when 1 is written to HALT, the bus operation is stopped (HALT = 1)
after transmission is completed. If reception is in progress when 1 is written to HALT, the bus
operation is stopped immediately (HALT = 1). If received messages are being stored in the
message buffer (x), the bus operation is stopped(HALT = 1) after storing the messages.
• To check whether the bus operation has stopped, always read the HALT bit.
n Conditions for canceling bus operation stop (HALT = 0)
• By writing 0 to HALT
Notes: • Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions
is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have
been input to the receive input pin (RX).
• Canceling the bus operation stop when the node status is changed to bus off as above conditions
is performed after 0 is written to HALT and continuous 11-bit High levels (recessive bits) have
been input 128 times to the receive input pin (RX). Then, the values of both transmit and receive
error counters reach 0 and the node status is changed to error active.
n State during bus operation stop (HALT = 1)
• The bus does not perform any operation, such as transmission and reception.
• The transmit output pin (TX) outputs a High level (recessive bit).
• The values of other registers and error counters are not changed.
Note:
The bit timing register (BTR) should be set during bus operation stop (HALT = 1).
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
23-14
2
MC-16LX is changed in

Advertisement

Table of Contents
loading

Table of Contents