Operation Of The I C Interface - Fujitsu F2MC-16LX Hardware Manual

19.4 Operation of the I
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The I C bus is used for communication with two bi-directional bus lines; one is a serial
data line (SDA) and the other is a serial clock line (SCL). The I
corresponding open drain input-output pins (SDA and SCL) to support the wired logic.
■ Start Condition
If 1 is written to the MSS bit when the bus is free (BB = 0 and MSS = 0), the I
master mode and the start condition is generated at the same time. In master mode, the start
condition can be regenerated by writing "1" to the SCC bit even if the bus is in use (BB = 1).
The start condition is generated in the two following ways:
1. Write "1" to the MSS bit when the bus is not in use (MSS = 0*BB = 0*INT = 0*AL = 0).
2. Write "1" to the SCC bit in the interrupt state in bus master mode (MSS = 1*BB = 1*INT =
1*AL = 0).
If "1" is written to the MSS bit when another system (being idle) is using the bus, the AL bit is set
to "1". In conditions other than the above 1) and 2), writing "1" to the MSS bit or the SCC bit is
ignored.
■ Stop Condition
Writing "0" to the MSS bit in master mode (MSS = 1) generates the stop condition, and the
mode switches to slave mode.
The condition necessary to generate the stop condition is as follows:
• Write "0" to the MSS bit in the interrupt state in bus master mode (MSS = 1*BB = 1*INT = 1*AL
= 0).
Under other conditions, writing "0" to the MSS bit is ignored.
■ Addressing
In master mode, after the start condition is generated, the BB and TRX bits are set to "1" and
the contents of the IDAR register are output starting from the MSB. When acknowledgment is
received from the slave after the address data is sent, bit0 of the send data (bit0 of the sent
IDAR register) is reversed and stored in the TRX bit.
In slave mode, after the start condition is generated, the BB bit is set to "1" and the TRX bit is
set to "0", and the send data from the master is received by the IDAR register. After the
address data is received, the IDAR register is compared with the IADR register. When a match
occurs, the AAS bit is set to "1" and the acknowledgment is sent to the master. bit0 of the
received data (bit0 of the received IDAR register) is then stored in the TRX bit.
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C Interface
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19.4 Operation of the I C Interface
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C interface has two
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C interface is in
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