Overview Of External Interrupt/Nmi Controller - Fujitsu MB91260B Series Hardware Manual

32-bit microcontroller
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CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
6.1

Overview of External Interrupt/NMI Controller

The external interrupt controller is a block that controls external interrupt requests input
to NMI and INT0 to INT9.
For external interrupt input, "H" level, "L" level, "rising edge", or "falling edge" can be
selected as the level of a request to be detected.
■ Register List
Following figure shows the register list of the external interrupt/NMI controller.
External interrupt source register
EIRR0 Address: 00000040
EIRR1 Address: 000000B8
Interrupt enable register
ENIR0 Address: 00000041
ENIR1 Address: 000000B9
External interrupt request level setting register
ELVR0 Address: 00000042
ELVR1 Address: 000000BA
ELVR0 Address: 00000043
ELVR1 Address: 000000BB
130
Bit No. →
7
6
ER7
ER6
ER5
H
H
Bit No. →
7
6
EN7
EN6
EN5
H
H
Bit No. →
15
14
LB7
LA7
LB6
H
H
Bit No. →
7
6
LB3
LA3
LB2
H
H
5
4
3
2
ER4
ER3
ER2
5
4
3
2
EN4
EN3
EN2
13
12
11
10
LA6
LB5
LA5
5
4
3
2
LA2
LB1
LA1
LB9
LA9
1
0
Initial value
00000000
[R/W]
ER1
ER0
B
- - - - - - 0 0
[R/W]
ER9
ER8
B
1
0
Initial value
00000000
[R/W]
EN1
EN0
B
- - - - - - 0 0
[R/W]
EN9
EN8
B
9
8
Initial value
00000000
[R/W]
LB4
LA4
B
- - - - - - - -
[R/W]
B
1
0
Initial value
00000000
[R/W]
LB0
LA0
B
----0000
[R/W]
LB8
LA8
B

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