External Memory Access; Block Diagram; Figure 3.2.1A External Bus Pin Control Circuit - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

3.2 External Memory Access

3.2 External Memory Access
To access external memory and peripherals, the F
control signals:
CLK
RDY
WRHX
WRLX
RDX
ALE
The external bus pin control circuit controls the external bus pins for externally extending the CPU
address/data bus.

3.2.1 Block diagram

RB
Access
control
36 Chapter 3: Memory
(P37) : Machine cycle clock (KBP)
(P36) : External ready input pin
(P33) : Write signal for high-order 8 bits of data bus
(P32) : Write signal for low-order 8 bits of data bus
(P31) : Read signal
(P30) : Address latch enable signal
P0
P0 data
P0 direction
Data control
Address
control
Access
control

Figure 3.2.1a External bus pin control circuit

2
MC-16LX supplies the following address, data, and
P3
P2
P1
P3
P0
MB90580 Series