R
Similarly, if RXUSRCLK is slower than RXRECCLK, the buffer fills up over time. The clock
correction logic corrects for this by incrementing the read pointer to skip over a removable
byte sequence that need not appear in the final FPGA core byte stream. This is shown in the
bottom buffer,
by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow.
The transceiver design skips a single byte sequence, when necessary, to partially empty a
buffer. If attribute CLK_COR_REPEAT_WAIT is 0, the transceiver can also skip two
consecutive removable byte sequences in one step, to further empty the buffer, when
necessary.
These operations require the clock correction logic to recognize a byte sequence that can be
freely repeated or omitted in the incoming data stream. This sequence is generally an IDLE
sequence, or other sequence comprised of special values that occur in the gaps separating
packets of meaningful data. These gaps are required to occur sufficiently often to facilitate
the timely execution of clock correction.
Channel Bonding
Some gigabit I/O standards such as Infiniband specify the use of multiple transceivers in
parallel for even higher data rates. Words of data are split into bytes, with each byte sent
over a separate channel (transceiver). See
The top half of the figure shows the transmission of words split across four transceivers
(channels or lanes). PPPP, QQQQ, RRRR, SSSS, and TTTT represent words sent over the
four channels.
The bottom-left portion of the figure shows the initial situation in the FPGA's receivers at
the other end of the four channels. Due to variations in transmission delay—especially if
the channels are routed through repeaters—the FPGA core might not correctly assemble
the bytes into complete words. The bottom-left illustration shows the incorrect assembly of
data words PQPP, QRQQ, RSRR, etc.
To support correction of this misalignment, the data stream includes special byte
sequences that define corresponding points in the several channels. In the bottom half of
Figure
22
Figure
2-2, where the solid read pointer increments to the value represented
Full word SSSS sent over four channels, one byte per channel
P Q R S T
P Q R S T
P Q R S T
P Q R S T
Read
RXUSRCLK
P Q R S T
P Q R S T
P Q R S T
P Q R S T
Before channel bonding
Figure 2-3: Channel Bonding (Alignment)
2-3, the shaded "P" bytes represent these special characters. Each receiver
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Chapter 2: RocketIO Transceiver Overview
Figure
2-3.
In Transmitters:
Channel (lane) 0
Channel (lane) 1
Channel (lane) 2
Channel (lane) 3
In Receivers:
Read
RXUSRCLK
P Q R S T
P Q R S T
P Q R S T
P Q R S T
After channel bonding
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide
DS083-2_16_010202