Enabling 8B/10B Mode; Using Comma Alignment; Fpga Rx Interface; Functional Description - Xilinx Virtex-6 FPGA User Manual

Chapter 4: Receiver

Enabling 8B/10B Mode

Follow these steps to enable the 8B/10B mode in the GTH receiver:
1.
2.
3.
4.

Using Comma Alignment

To enable the comma alignment block, the RXENCOMMADET port must be asserted.
When comma detection is enabled, the decoder sees a comma character at any bit position.
It tries to find the comma characters K28.1, K.28.5, and K28.7. When any of those comma
characters is found, the decoder locks to it. When RXENCOMMADET is deasserted, the
current state of the symbol lock remains unchanged.
If the comma characters can arrive in both even and odd byte positions, comma detection
should be disabled when symbol lock is achieved. The comma detection logic always
attempts to align comma characters to the least significant byte.

FPGA RX Interface

Functional Description

The FPGA receives RX data from the GTH receiver through the FPGA RX interface. Data is
read from the RXDATA port on the positive edge of RXUSERCLKIN. The width of the port
can be configured depending on the mode chosen (see
Table 4-19: FPGA RX Interface Port Width
The rate of the parallel clock, RXUSERCLKIN, at the interface is determined by the RX line
rate, the width of the RXDATA port, and whether or not 8B/10B mode is used. A block
inside the PCS handles the mapping of the internal data width to the fabric data width
selected in the design.
130
Set PCS_MODE_LANE<n>[7:4] to 4'b0111.
Set PCS_RESET_LANE<n> to 0xFC5B.
Set PCS_RESET_1_LANE<n>[1:0] to 2'b00.
Set RX_FABRIC_WIDTH<n> to "16", "32", or "64" depending on the application.
Mode
8B/10B mode • 16 bits
• 32 bits
• 64 bits
64B/66 mode • 64 bits
Raw mode • 16 bits
• 20 bits
• 32 bits
• 40 bits
• 64 bits
• 80 bits
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Table
Port Width
Virtex-6 FPGA GTH Transceivers User Guide
4-19).
UG371 (v2.0) February 16, 2010