E.1.1.4 Floating-Point Status And Control Register (Fpscr) - Motorola MPC8240 User Manual

PowerPC Register Set

E.1.1.4 Floating-Point Status and Control Register (FPSCR)

The FPSCR is shown in Figure E-5.
VXIDI
VXISI
VXSNAN
FX FEX VX OX UX ZX XX
0 1 2 3 4 5 6
Figure E-5. Floating-Point Status and Control Register (FPSCR)
A listing of FPSCR bit settings is shown in Table E-4.
Bit(s) Name
0 FX Floating-point exception summary. Every floating-point instruction, except mtfsfi and mtfsf,
implicitly sets FPSCR[FX] if that instruction causes any of the floating-point exception bits in the
FPSCR to transition from 0 to 1. The mcrfs, mtfsfi, mtfsf, mtfsb0, and mtfsb1 instructions can
alter FPSCR[FX] explicitly. This is a sticky bit.
1 FEX Floating-point enabled exception summary. This bit signals the occurrence of any of the
enabled exception conditions. It is the logical OR of all the floating-point exception bits masked
by their respective enable bits (FEX = (VX & VE) ^ (OX & OE) ^ (UX & UE) ^ (ZX & ZE) ^ (XX &
XE)). The mcrfs, mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot alter FPSCR[FEX]
explicitly. This is not a sticky bit.
2 VX Floating-point invalid operation exception summary. This bit signals the occurrence of any
invalid operation exception. It is the logical OR of all of the invalid operation exceptions. The
mcrfs, mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot alter FPSCR[VX] explicitly. This
is not a sticky bit.
3 OX Floating-point overflow exception. This is a sticky bit.
4 UX Floating-point underflow exception. This is a sticky bit.
5 ZX Floating-point zero divide exception. This is a sticky bit.
6 XX Floating-point inexact exception. This is a sticky bit.
FPSCR[XX] is the sticky version of FPSCR[FI]. The following rules describe how FPSCR[XX] is
set by a given instruction:
• If the instruction affects FPSCR[FI], the new value of FPSCR[XX] is obtained by logically
ORing the old value of FPSCR[XX] with the new value of FPSCR[FI].
• If the instruction does not affect FPSCR[FI], the value of FPSCR[XX] is unchanged.
7 VXSNAN Floating-point invalid operation exception for SNaN. This is a sticky bit.
8 VXISI Floating-point invalid operation exception for ∞ – ∞. This is a sticky bit.
9 VXIDI Floating-point invalid operation exception for ∞ ÷ ∞. This is a sticky bit.
10 VXZDZ Floating-point invalid operation exception for 0 ÷ 0. This is a sticky bit.
11 VXIMZ Floating-point invalid operation exception for ∞ * 0. This is a sticky bit.
12 VXVC Floating-point invalid operation exception for invalid compare. This is a sticky bit.
13 FR Floating-point fraction rounded. The last arithmetic or rounding and conversion instruction that
rounded the intermediate result incremented the fraction. This bit is not sticky.
E-6
FR FI
7 8 9 10 11 12 13 14 15
Table E-4. FPSCR Bit Settings
MPC8240 Integrated Processor User's Manual
VXZDZ
VXIMZ
VXVC
FPRF 0
19 20 21 22 23 24 25 26 27 28 29 30
Description
Reserved
VXSOFT
VXSQRT
VXCVI
VE OE UE ZE XE NI RN
31