Table 99. Quadspi Pins; Figure 58. Quadspi Block Diagram When Dual-Flash Mode Is Disabled; Figure 59. Quadspi Block Diagram When Dual-Flash Mode Is Enabled - ST STM32L4 5 Series Reference Manual

RM0351
17.4 QUADSPI functional description
17.4.1 QUADSPI block diagram
17.4.2 QUADSPI pins
Table 99
for interfacing with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode.
Signal name
CLK
BK1_IO0/SO
BK1_IO1/SI

Figure 58. QUADSPI block diagram when dual-flash mode is disabled

Figure 59. QUADSPI block diagram when dual-flash mode is enabled

lists the QUADSPI pins, six for interfacing with a single Flash memory, or 10 to 11
Signal type
Digital output
Digital input/output
Digital input/output

Table 99. QUADSPI pins

Clock to FLASH 1 and FLASH 2
Bidirectional IO in dual/quad modes or serial output
in single mode, for FLASH 1
Bidirectional IO in dual/quad modes or serial input
in single mode, for FLASH 1
DocID024597 Rev 5
Quad-SPI interface (QUADSPI)
Description
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