Table 2.12 Registers With Shared Addresses - Renesas H8/3847R Series Hardware Manual

Section 2 CPU
[B: BCLR instruction executed]
BCLR #0 ,
[C: After executing BCLR]
MOV. B @RAM0,
MOV. B R0L,
P3
7
Input/output Input
Pin state Low
level
PCR3 0
PDR3 1
RAM0 0
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.

Table 2.12 Registers with Shared Addresses

Register Name
Timer counter and timer load register C
Port data register 1 *
Port data register 2 *
Port data register 3 *
Port data register 4 *
Port data register 5 *
Port data register 6 *
Port data register 7 *
Port data register 8 *
Port data register 9 *
Port data register A *
Note: * Port data registers have the same addresses as input pins.
Rev. 6.00 Aug 04, 2006 page 90 of 680
REJ09B0145-0600
The BCLR instruction is executed designating the PCR3
@RAM0
work area (RAM0).
The work area (RAM0) value is written to PCR3.
R0L
@PCR3
P3 P3
6 5
Input Output
High Low
level level
0 1
0 0
0 1
P3 P3 P3
4 3
Output Output Output
Low Low Low
level level level
1 1 1
0 0 0
1 1 1
Abbr.
TCC/TLC
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
P3 P3
2 1 0
Output Output
Low High
level level
1 0
0 0
1 0
Address
H'FFB5
H'FFD4
H'FFD5
H'FFD6
H'FFD7
H'FFD8
H'FFD9
H'FFDA
H'FFDB
H'FFDC
H'FFDD