Timer Operation - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

4. Port Mode Register 3 (PMR3)

Initial value

PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3

pins. Only the bit relating to the watchdog timer is described here. For details of the other bits,

see section 8, I/O Ports.

Bit 5: Watchdog timer source clock select (WDCKS)

φ/8192 selected

φw/32 selected

Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (φ/8192 or

φw/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): φ/8192 is

selected when WDCKS is cleared to 0, and φw/32 when set to 1. When TCSRWE = 1 in TCSRW,

if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When

the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow,

and an internal reset signal is generated one base clock (φ or φ

signal is output for 512 clock cycles of the φ

TCW to count up from the written value. The overflow period can be set in the range from 1 to

256 input clocks, depending on the value written in TCW.

clock. It is possible to write to TCW, causing

) cycle later. The internal reset

Rev. 6.00 Aug 04, 2006 page 317 of 680

Section 9 Timers

(initial value)

REJ09B0145-0600