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Appendix B Internal I/O Registers
SYSCR1—System Control Register 1
Bit
7
SSBY
Initial value
0
Read/Write
R/W
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
1
Rev. 6.00 Aug 04, 2006 page 620 of 680
REJ09B0145-0600
6
5
STS2
STS1
0
0
R/W
R/W
Standby timer select 2 to 0
0
0 0
1 0
0 0
1
1 0
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
• When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
H'F0
4
3
STS0
LSON
0
0
R/W
R/W
Low speed on flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ
Wait time = 8,192 states
1
Wait time = 16,384 states
Wait time = 32,768 states
1
Wait time = 65,536 states
Wait time = 131,072 states
1
Wait time = 2 states
Wait time = 8 states
1
Wait time = 16 states
System control
2
1
0
MA1
MA0
1
1
1
R/W
R/W
Active (medium-speed)
mode clock select
φ
0
0
/16
osc
φ
1
/32
osc
φ
/64
1
0
osc
φ
/128
1
osc
SUB
)
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