Renesas H8/3847R Series Hardware Manual page 27

Figure 9.2 Block Diagram of Timer C ................................................................................ 267
Figure 9.3 Block Diagram of Timer F ................................................................................ 276
Write Access to TCR (CPU → TCF) ................................................................ 286
Figure 9.4
Read Access to TCF (TCF → CPU).................................................................. 287
Figure 9.5
Figure 9.6 TMOFH/TMOFL Output Timing...................................................................... 289
Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal
is Valid .............................................................................................................. 293
Figure 9.8 Block Diagram of Timer G................................................................................ 295
Figure 9.9 Noise Canceler Block Diagram ......................................................................... 301
Figure 9.10 Noise Canceler Timing (Example) .................................................................... 302
Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)................. 304
Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function)...................... 304
Figure 9.13 Timing of Input Capture by Input Capture Input............................................... 305
Figure 9.14 TCG Clear Timing............................................................................................. 305
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure........................................................................................................... 310
Figure 9.16 Timer G Application Example........................................................................... 311
Figure 9.17 Block Diagram of Watchdog Timer .................................................................. 312
Figure 9.18 Typical Watchdog Timer Operations (Example)............................................... 318
Figure 9.19 Block Diagram of Asynchronous Event Counter .............................................. 321
Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit
Event Counter .................................................................................................... 327
Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters............................................................................................................. 328
Section 10 Serial Communication Interface
Figure 10.1 SCI1 Block Diagram ......................................................................................... 333
Figure 10.2 Transfer Format ................................................................................................. 340
Figure 10.3 Example of SSB Connections............................................................................ 343
Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1) .......................... 344
Figure 10.5 HOLD TAIL and LATCH TAIL Output Waveforms ....................................... 344
Figure 10.6 SCI3 Block Diagram ......................................................................................... 349
Figure 10.7 (a) RDRF Setting and RXI Interrupt....................................................................... 378
Figure 10.7 (b) TDRE Setting and TXI Interrupt ....................................................................... 378
Figure 10.7 (c) TEND Setting and TEI Interrupt ....................................................................... 378
Figure 10.8 Data Format in Asynchronous Communication ................................................ 379
Figure 10.9 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)....................................... 381
Figure 10.10 Example of SCI3 Initialization Flowchart ......................................................... 382
Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode).................... 383
Rev. 6.00 Aug 04, 2006 page xxv of xxxvi