Renesas H8/3847R Series Hardware Manual page 592

Appendix A CPU Instruction Set
Table A.3 Number of Cycles in Each Instruction
Execution Status
(instruction cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data
Access for details.
Rev. 6.00 Aug 04, 2006 page 554 of 680
REJ09B0145-0600
Access Location
On-Chip Memory
S 2
I
S
J
S
K
S
L
S
M
S 1
N
On-Chip Peripheral Module
—
2 or 3 *
—