Renesas H8/3847R Series Hardware Manual page 307

Bits 6 and 5: Counter up/down control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6 Bit 5
TMC6 TMC5
0 0
0 1
1 *
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2 Bit 1
TMC2 TMC1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See 1. IRQ edge select register (IEGR) in section 3.3.2 for details.
IRQ1 must be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2
to TMC0.
Description
TCC is an up-counter
TCC is a down-counter
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
Bit 0
TMC0 Description
Internal clock: φ/8192
0
Internal clock: φ/2048
1
Internal clock: φ/512
0
Internal clock: φ/64
1
Internal clock: φ/16
0
Internal clock: φ/4
1
Internal clock: φ
0
1 External event (TMIC): rising or falling edge*
/4
W
Rev. 6.00 Aug 04, 2006 page 269 of 680
Section 9 Timers
(initial value)
*: Don't care
(initial value)
REJ09B0145-0600