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When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input Capture Register GF (ICRGF)
7
Bit:
ICRGF7
Initial value:
0
Read/Write:
R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
ICRGF is initialized to H'00 upon reset.
3. Input Capture Register GR (ICRGR)
7
Bit:
ICRGR7
Initial value:
0
Read/Write:
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φ
6
5
ICRGF6
ICRGF5
0
0
R
R
(when the noise canceler is not used).
SUB
6
5
ICRGR6
ICRGR5
0
0
R
R
(when the noise canceler is not used).
SUB
4
3
ICRGF4
ICRGF3
ICRGF2
0
0
R
R
4
3
ICRGR4
ICRGR3
ICRGR2
0
0
R
R
Rev. 6.00 Aug 04, 2006 page 297 of 680
Section 9 Timers
2
1
0
ICRGF1
ICRGF0
0
0
0
R
R
R
2
1
0
ICRGR1
ICRGR0
0
0
0
R
R
R
REJ09B0145-0600
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