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Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation settling time.
Bit 6
Bit 5
STS2
STS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Note: When inputting the external clock, set the standby timer select to the external clock input
mode. Also, when not using the external clock, do not set the standby timer select to the
external clock input mode.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (φ) or subclock (φ
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (φ)
1
The CPU operates on the subclock (φ
Bits 2: Reserved bits
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Bit 4
STS0
Description
0
Wait time = 8,192 states
1
Wait time = 16,384 states
0
Wait time = 32,768 states
1
Wait time = 65,536 states
0
Wait time = 131,072 states
1
Wait time = 2 states
0
Wait time = 8 states
1
Wait time = 16 states
Section 5 Power-Down Modes
(External clock input mode)
) as the CPU operating clock when watch
SUB
)
SUB
Rev. 6.00 Aug 04, 2006 page 135 of 680
(initial value)
(initial value)
REJ09B0145-0600
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