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Appendix B Internal I/O Registers
IRR2—Interrupt Request Register 2
Bit
Initial value
Read/Write
A/D converter interrupt request flag
0 [Clearing condition]
When IRRAD = 1, it is cleared by writing 0
1 [Setting condition]
When the A/D converter completes conversion and
ADSF is reset
Direct transition interrupt request flag
0 [Clearing condition]
When IRRDT = 1, it is cleared by writing 0
1 [Setting condition]
When a SLEEP instruction is executed while DTON is
set to 1, and a direct transition is made
Note: * Bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 626 of 680
REJ09B0145-0600
7
6
5
IRRDT
IRRAD
—
IRRTG
0
0
0
R/(W)*
R/(W)*
R/W
R/(W)*
Timer C interrupt request flag
Timer FL interrupt request flag
0 [Clearing condition]
When IRRTFL = 1, it is cleared by writing 0
1 [Setting condition]
When counter FL and output compare register FL
match in 8-bit timer mode
Timer FH interrupt request flag
0 [Clearing condition]
When IRRTFH = 1, it is cleared by writing 0
1 [Setting condition]
When counter FH and output compare register FH match
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
Timer G interrupt request flag
0 [Clearing condition]
When IRRTG = 1, it is cleared by writing 0
1 [Setting condition]
When the TMIG pin is designated for TMIG input and
the designated signal edge is input
4
3
2
1
IRRTFH
IRRTFL
IRRTC
0
0
0
0
R/(W)*
R/(W)*
R/(W)*
Asynchronous event counter interrupt request flag
0 [Clearing condition]
When IRREC = 1, it is cleared by writing 0
1 [Setting condition]
When the asynchronous event counter value overflows
0 [Clearing condition]
When IRRTC = 1, it is cleared by writing 0
1 [Setting condition]
When the timer C counter value overflows
(from H'FF to H'00) or underflows (from H'00 to H'FF)
H'F7
System control
0
IRREC
0
R/(W)*
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