Renesas H8/3847R Series Hardware Manual page 595

8-bit single-chip microcomputer super low power
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Instruc-
tion
Mnemonic
BTST
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
CMP
CMP. B #xx:8, Rd
CMP. B Rs, Rd
CMP.W Rs, Rd
DAA
DAA.B Rd
DAS
DAS.B Rd
DEC
DEC.B Rd
DIVXU
DIVXU.B Rs, Rd
EEPMOV
EEPMOV
INC
INC.B Rd
JMP
JMP @Rn
JMP @aa:16
JMP @@aa:8
JSR
JSR @Rn
JSR @aa:16
JSR @@aa:8
LDC
LDC #xx:8, CCR
LDC Rs, CCR
MOV
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16, Rs),
Rd
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
Instruction
Branch
Fetch
Addr. Read
I
J
1
2
2
1
2
2
1
2
2
1
1
1
1
1
1
1
2
1
2
2
2
1
2
2
2
1
1
1
1
1
1
2
1
1
2
1
Appendix A CPU Instruction Set
Stack
Byte Data
Word Data
Operation
Access
Access
K
L
M
1
1
1
1
1
1
2n+2 *
1
1
1
1
1
1
1
1
1
1
Rev. 6.00 Aug 04, 2006 page 557 of 680
Internal
Operation
N
12
1 *
2
2
2
2
2
REJ09B0145-0600

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