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Section 9 Timers
2. Event Counter H (ECH)
Bit
7
ECH7
Initial Value
0
Read/Write
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source by bit CH2. ECH can be cleared to H'00 by
software, and is also initialized to H'00 upon reset.
3. Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin is used as the input clock source.
ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Bit
7
ECL7
Initial Value
0
Read/Write
R
4. Clock Stop Register 2 (CKSTPR2)
Bit
7
—
Initial value
1
Read/Write
—
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Rev. 6.00 Aug 04, 2006 page 326 of 680
REJ09B0145-0600
6
5
ECH6
ECH5
ECH4
0
0
R
R
6
5
ECL6
ECL5
ECL4
0
0
R
R
6
5
—
—
1
1
—
—
—
4
3
ECH3
ECH2
0
0
R
R
4
3
ECL3
ECL2
0
0
R
R
4
3
—
AECKSTP
WDCKSTP PWCKSTP LDCKSTP
1
1
R/W
R/W
2
1
ECH1
ECH0
0
0
R
R
2
1
ECL1
ECL0
0
0
R
R
2
1
0
1
1
1
R/W
R/W
0
0
R
0
0
R
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