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Section 9 Timers
Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
Bit 2
CCLR1
CCLR0
0
0
0
1
1
0
1
1
Bits 1 and 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
Bit 0
CKS1
CKS0
0
0
0
1
1
0
1
1
5. Clock Stop Register 1 (CKSTPR1)
Bit:
7
S1CKSTP
Initial value:
1
Read/Write:
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
Rev. 6.00 Aug 04, 2006 page 300 of 680
REJ09B0145-0600
Description
TCG clearing is disabled
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
Description
Internal clock: counting on φ/64
Internal clock: counting on φ/32
Internal clock: counting on φ/2
Internal clock: counting on φw/4
6
5
S31CKSTP S32CKSTP ADCKSTP TGCKSTP
1
1
R/W
R/W
4
3
TFCKSTP TCCKSTP TACKSTP
1
1
R/W
R/W
R/W
(initial value)
(initial value)
2
1
0
1
1
1
R/W
R/W
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