Timer Operation - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Section 9 Timers

4. Subclock Output Select Register (CWOSR)

Initial value:

CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin.

CWOSR is initialized to H'FE by a reset.

Bits 7 to 1: Reserved bits

Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified.

Bit 0: TMOW pin clock select (CWOS)

Bit 0 selects the clock to be output from the TMOW pin.

Clock output from timer A is output (see TMA)

Timer Operation

1. Interval Timer Operation

When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit

interval timer.

Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval

timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in

TMA; any of eight internal clock signals output by prescaler S can be selected.

After the count value in TCA reaches H'FF, the next clock signal input causes timer A to

overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt

enable register 1 (IENR1), a CPU interrupt is requested.*

At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as

an interval timer that generates an overflow output at intervals of 256 input clock pulses.

Rev. 6.00 Aug 04, 2006 page 264 of 680

REJ09B0145-0600

(initial value)