Renesas H8/3847R Series Hardware Manual page 446

Section 10 Serial Communication Interface
9. Cautions on Switching of SCK
If the function of the SCK
clock synchronization mode, the "low" level is output in a moment (1/2 of the system clock φ) at
the SCK pin function switching.
3X
This momentary "low" level output can be avoided in either of the following two methods:
a. When disabling SCK
When stopping signal transmission, clear the bits TE and RE in SCR3, and set the CKE1
bit to "1" and the CKE0 bit to "0" simultaneously with a single command.
In this case, use the COM bit in SMR set at "1". This means it cannot be used as an I/O
port. Also, to avoid intermediate potential from being applied to the SCK
line connected to the SCK
from other devices.
b. When switching the SCK
When stopping signal transmission,
(1) Clear the bits TE and RE in SCR3, and set the CKE1 bit to "1" and the CKE0 bit to "0"
simultaneously with a single command.
(2) Then, clear the COM bit in SMR to "0".
(3) Finally, clear the bits CKE1 and CKE0 in SCR3 to "0". Avoid intermediate potential
from being applied to the SCK
10. Setting in Subactive and Subsleep Modes
In subactive or subsleep mode, SCI3 can be used only when the φ
Set the SA1 bit in SYSCR2 to "1".
Rev. 6.00 Aug 04, 2006 page 408 of 680
REJ09B0145-0600
Pin Function
3X
pin is switched from clock output to I/O port after using the SCI3 in
3X
pin clock output
3X
pin to V potential with a resistance, or supply an output
3X CC
pin function from clock output to I/O port
3X
pin.
3X
pin, pull up the
3X
/2 is selected as the CPU clock.
W