Renesas H8/3847R Series Hardware Manual page 395

Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE Description
0 Transmit data empty interrupt request (TXI) disabled
1 Transmit data empty interrupt request (TXI) enabled
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing
bit RIE to 0.
Bit 6
RIE Description
0 Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1 Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
Section 10 Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 357 of 680
(initial value)
(initial value)
REJ09B0145-0600