Renesas H8/3847R Series Hardware Manual page 396

Section 10 Serial Communication Interface
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE Description
Transmit operation disabled *
0
Transmit operation enabled *
1
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE Description
Receive operation disabled *
0
Receive operation enabled *
1
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Rev. 6.00 Aug 04, 2006 page 358 of 680
REJ09B0145-0600
1
(TXD pin is I/O port)
2
(TXD pin is transmit data pin)
1
(RXD pin is I/O port)
2
(RXD pin is receive data pin)
(initial value)
(initial value)