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ECCSR—Event Counter Control/Status Register
Bit
Initial value
Read/Write
Counter overflow H
0
1
Note: * Only a write of 0 for clearing is possible.
7
6
5
OVH
OVL
0
0
0
R/(W) *
R/(W) *
R/W
Counter overflow L
0 ECL has not overflowed
Clearing condition:
After readng OVL = 1, cleared by writing 0 to OVL
1 ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
ECH has not overflowed
Clearing condition:
After readng OVH = 1, cleared by writing 0 to OVH
ECH has overflowed
Setting condition:
Set when ECH overflows from H'FF to H'00
Appendix B Internal I/O Registers
4
3
2
CH2
CUEH
CUEL
0
0
0
R/W
R/W
R/W
Counter reset control L
Counter reset control H
0
ECH is reset
1
ECH reset is cleared and
count-up function is enabled
Count-up enable L
0
ECL event clock input is disabled.
ECL value is held
1
ECL event clock input is enabled
Count-up enable H
0
ECH event clock input is disabled.
ECH value is held
1
ECH event clock input is enabled
Channel select
0
ECH and ECL are used together as a single-
channel 16-bit event counter
1
ECH and ECL are used as two independent
8-bit event counter channels
Rev. 6.00 Aug 04, 2006 page 571 of 680
H'95
1
0
CRCH
CRCL
0
0
R/W
R/W
0
ECL is reset
1
ECL reset is cleared
and count-up function
is enabled
REJ09B0145-0600
AEC
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