Asynchronous Event Counter Operation Modes; Application Notes; Table 9.21 Asynchronous Event Counter Operation Modes - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Asynchronous Event Counter Operation Modes

Asynchronous event counter operation modes are shown in table 9.21.

* When an asynchronous external event is input, the counter increments but the counter

overflow H/L flags are not affected.

1. When reading the values in ECH and ECL, the correct value will not be returned if the event

counter increments during the read operation. Therefore, if the counter is being used in the 8-

bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the

counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.

2. In the H8/3847R Group, if the internal power supply step-down circuit is not used, the

maximum clock frequency to be input to the AEVH and AEVL pins is 16 MHz when Vcc =

4.5 to 5.5 V, 10 MHz when Vcc = 2.7 to 5.5 V, and 4 MHz when Vcc = 1.8 to 5.5 V. If the

internal power step-down circuit is used, the maximum clock frequency to be input is 10 MHz

when Vcc = 2.7 to 5.5 V, and 4 MHz when Vcc = 1.8 to 5.5 V. In the H8/3847S Group, the

maximum clock frequency to be input is 10 MHz when Vcc = 2.7 to 3.6 V, and 4 MHz when

Vcc = 1.8 to 3.6 V. In the H8/38347 Group and H8/38447 Group, the maximum clock

frequency to be input is 16 MHz when Vcc = 2.7 to 5.5 V. In addition, ensure that the high and

low widths of the clock are at least 32 ns. The duty cycle is immaterial.

Functions* Functions

Functions* Functions

Subactive Subsleep

Rev. 6.00 Aug 04, 2006 page 329 of 680

Section 9 Timers

Functions* Halted

REJ09B0145-0600