Renesas H8/3847R Series Hardware Manual page 24

Section 1 Overview
Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group) ................................
Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group) .................................
Figure 1.2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View) ................ 10
Figure 1.3 Pin Arrangement (FP-100A: Top View) ........................................................... 11
Figure 1.4 Bonding Pad Location Diagram of H8/3847R Group (Mask ROM Version)
(Top View) ........................................................................................................ 12
Figure 1.5 Bonding Pad Location Diagram of H8/3847S Group (Mask ROM Version)
(Top View) ........................................................................................................ 17
Figure 1.6 Bonding Pad Location Diagram of HCD64F38347 and HCD64F38447
(Top View) ........................................................................................................ 22
Figure 1.7 Bonding Pad Location Diagram of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version) (Top View).................................. 27
Section 2 CPU
Figure 2.1 CPU Registers ................................................................................................... 41
Figure 2.2 Stack Pointer...................................................................................................... 42
Figure 2.3 Register Data Formats ....................................................................................... 45
Figure 2.4 Memory Data Formats....................................................................................... 46
Figure 2.5 Data Transfer Instruction Codes........................................................................ 56
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes ................................................. 60
Figure 2.7 Bit Manipulation Instruction Codes................................................................... 63
Figure 2.8 Branching Instruction Codes ............................................................................. 66
Figure 2.9 System Control Instruction Codes ..................................................................... 68
Figure 2.10 Block Data Transfer Instruction Code ............................................................... 69
Figure 2.11 On-Chip Memory Access Cycle........................................................................ 70
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)............................. 71
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)............................. 72
Figure 2.14 CPU Operation States........................................................................................ 74
Figure 2.15 State Transitions ................................................................................................ 75
Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map .......................................... 77
Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map .......................................... 78
Figure 2.16 (3) H8/3844R, H8/3844S, H8/38344 and H8/38444 Memory Map ........................ 79
Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map ........................ 80
Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map ........................ 81
Figure 2.16 (6) H8/3847R, H8/3847S, H8/38347 and H8/38447 Memory Map ........................ 82
Rev. 6.00 Aug 04, 2006 page xxii of xxxvi
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