Renesas H8/3847R Series Hardware Manual page 320

Section 9 Timers
4. Timer Control/Status Register F (TCSRF)
Bit:
7
OVFH
Initial value:
0
Read/Write: R/(W) *
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH Description
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCFH overflows from H'FF to H'00
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH Description
0 Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1 Setting condition:
Set when the TCFH value matches the OCRFH value
Rev. 6.00 Aug 04, 2006 page 282 of 680
REJ09B0145-0600
6 5
CMFH OVIEH CCLRH
0 0
R/(W) *
R/W
4 3
OVFL CMFL
0 0
R/(W) * R/(W) *
R/W
2 1 0
OVIEL CCLRL
0 0 0
R/W R/W
(initial value)
(initial value)