Renesas H8/3847R Series Hardware Manual page 337

Bit 6: Timer overflow flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL Description
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCG overflows from H'FF to H'00
Bit 5: Timer overflow interrupt enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE Description
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
Bit 4: Input capture interrupt edge select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS Description
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
Rev. 6.00 Aug 04, 2006 page 299 of 680
Section 9 Timers
(initial value)
(initial value)
(initial value)
REJ09B0145-0600