Renesas H8/3847R Series Hardware Manual page 593

Table A.4 Number of Cycles in Each Instruction
Instruc-
tion Mnemonic
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS ADDS.W #1, Rd
ADDS.W #2, Rd
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC ANDC #xx:8, CCR
BAND BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa: 8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
Instruction Branch
Fetch Addr. Read
I J
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
Appendix A CPU Instruction Set
Stack Byte Data Word Data
Operation Access Access
K L M
1
1
2
2
2
2
Rev. 6.00 Aug 04, 2006 page 555 of 680
Internal
Operation
N
REJ09B0145-0600