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Section 9 Timers
2. Timer Counter C (TCC)
Bit
7
TCC7
Initial value
0
Read/Write
R
TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode
register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
3. Timer Load Register C (TLC)
Bit
7
TLC7
Initial value
0
Read/Write
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up from that value. When TCC overflows or underflows during operation in auto-
reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow periods can be
set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
Rev. 6.00 Aug 04, 2006 page 270 of 680
REJ09B0145-0600
6
5
TCC6
TCC5
TCC4
0
0
R
R
6
5
TLC6
TLC5
TLC4
0
0
W
W
4
3
2
TCC3
TCC2
0
0
0
R
R
R
4
3
2
TLC3
TLC2
0
0
0
W
W
W
1
0
TCC1
TCC0
0
0
R
R
1
0
TLC1
TLC0
0
0
W
W
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