Renesas H8/3847R Series Hardware Manual page 29

Figure 13.5 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty) ............. 444
Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) ............. 445
Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) ............. 446
Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode) ........ 447
Figure 13.9 LCD RAM Map with Segment Externally Expanded
(SGX = "1", SGS3 to SGS0 = "0000" 1/4 duty) ............................................... 448
Figure 13.10 LCD RAM Map with Segment Externally Expanded
(SGX = "1", SGS3 to SGS0 = "0000" 1/3 duty) ............................................... 449
Figure 13.11 LCD RAM Map with Segment Externally Expanded
(SGX = "1", SGS3 to SGS0 = "0000" 1/2 duty) ............................................... 450
Figure 13.12 LCD RAM Map with Segment Externally Expanded
(SGX = "1", SGS3 to SGS0 = "0000" static) .................................................... 451
Figure 13.13 LCD Drive Power Supply Unit.......................................................................... 452
Figure 13.14 Example of Low-Power-Consumption LCD Drive Operation .......................... 454
Figure 13.15 Output Waveforms for Each Duty Cycle (A Waveform) .................................. 455
Figure 13.16 Output Waveforms for Each Duty Cycle (B Waveform) .................................. 456
Figure 13.17 Connection of External Split-Resistance ........................................................... 458
Figure 13.18 Connection to HD66100.................................................................................... 460
Section 14 Power Supply Circuit
Figure 14.1 Power Supply Connection when Internal Step-Down Circuit is Used .............. 461
Figure 14.2 Power Supply Connection when Internal Step-Down Circuit is Not Used........ 462
Section 15 Electrical Characteristics
Figure 15.1 Clock Input Timing ........................................................................................... 535
RES Low Width ................................................................................................ 535
Figure 15.2
Figure 15.3 Input Timing...................................................................................................... 535
Figure 15.4 UD Pin Minimum Modulation Width Timing ................................................... 536
Figure 15.5 SCI1 Input/Output Timing................................................................................. 536
Figure 15.6 SCK3 Input Clock Timing................................................................................. 537
Figure 15.7 SCI3 Synchronous Mode Input/Output Timing................................................. 537
Figure 15.8 Segment Expansion Signal Timing.................................................................... 538
Figure 15.9 Output Load Condition...................................................................................... 539
Figure 15.10 Resonator Equivalent Circuit............................................................................. 540
Figure 15.11 Recommended Resonators................................................................................. 540
Appendix C I/O Port Block Diagrams
Figure C.1 (a) Port 1 Block Diagram (Pins P1
Figure C.1 (b) Port 1 Block Diagram (Pin P1
Figure C.1 (c) Port 1 Block Diagram (Pin P1
to P1 ) ............................................................ 630
7 4
)......................................................................... 631
3
, P1 ) ................................................................. 632
2 1
Rev. 6.00 Aug 04, 2006 page xxvii of xxxvi