Renesas H8/3847R Series Hardware Manual page 140

Section 3 Exception Handling
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC Description
0 Disables asynchronous event counter interrupt requests
1 Enables asynchronous event counter interrupt requests
For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in
section 10.3.2.
4. Interrupt Request Register 1 (IRR1)
Bit 7
IRRTA
Initial value 0
R/(W) *
Read/Write
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ to IRQ
4
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA Description
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1 Setting condition:
When the timer A counter value overflows from H'FF to H'00
Rev. 6.00 Aug 04, 2006 page 102 of 680
REJ09B0145-0600
6 5
IRRS1 —
0 1
R/(W) *
—
interrupt is requested. The flags are not cleared automatically when an
0
4 3
IRRI4 IRRI3 IRRI2
0 0
R/(W) * R/(W) * R/(W) *
(initial value)
2 1 0
IRRI1 IRRI0
0 0 0
R/(W) * R/(W) *
(initial value)