Table of Contents
Advertisement
Appendix B Internal I/O Registers
TCSRW—Timer Control/Status Register W
Bit
Initial value
Read/Write
Bit 2 write inhibit
0 Bit 2 is write-enabled
1
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1
Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1
Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1
Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
Rev. 6.00 Aug 04, 2006 page 590 of 680
REJ09B0145-0600
7
6
5
B6WI
TCWE
B4WI
1
0
1
*
R
R/(W)
R
Watchdog timer reset
0 [Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1
Bit 0 is write-protected
Watchdog timer on
0 Watchdog timer operation is disabled
1
Watchdog timer operation is enabled
Bit 2 is write-protected
H'B2
4
3
TCSRWE
B2WI
WDON
0
1
*
R/(W)
R
R/(W)
Watchdog timer
2
1
0
B0WI
WRST
0
1
0
*
R
R/(W)
*
Advertisement
Table of Contents
