Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) - Renesas H8/3847R Series Hardware Manual

Section 2 CPU
Three-state access to on-chip peripheral modules
φ or φ
SUB
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)

Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)

Rev. 6.00 Aug 04, 2006 page 72 of 680
REJ09B0145-0600
Bus cycle
T state
1
Address
T state
2
Read data
Write data
T state
3