Timer C Operation States; Table 9.7 Timer C Operation States - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Timer C Operation States

Table 9.7 summarizes the timer C operation states.

Timer C Operation States

Operation Mode

* When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since

the system clock and internal clock are mutually asynchronous, synchronization is

maintained by a synchronization circuit. This results in a maximum count cycle error of

1/φ (s). When the counter is operated in subactive mode or subsleep mode, either

select φw/4 as the internal clock or select an external clock. The counter will not

operate on any other internal clock. If φw/4 is selected as the internal clock for the

counter when φw/8 has been selected as subclock φ

operate on the same cycle, and the operation of the least significant bit is unrelated to

the operation of the counter.

Functions Functions Halted

Functions Retained

Functions Retained

, the lower 2 bits of the counter

Rev. 6.00 Aug 04, 2006 page 273 of 680

Section 9 Timers

REJ09B0145-0600