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Section 9 Timers
2. Timer Counter W (TCW)
Bit
7
TCW7
Initial value
0
Read/Write
R/W
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is φ/8192 or φw/32. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
3. Clock Stop Register 2 (CKSTPR2)
Bit
7
—
Initial value
1
Read/Write
—
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2: Watchdog timer module standby mode control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP
Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
Rev. 6.00 Aug 04, 2006 page 316 of 680
REJ09B0145-0600
6
5
TCW6
TCW5
TCW4
0
0
R/W
R/W
6
5
—
—
—
1
1
—
—
—
4
3
2
TCW3
TCW2
0
0
0
R/W
R/W
R/W
4
3
2
AECKSTP
WDCKSTP PWCKSTP LDCKSTP
1
1
1
R/W
R/W
1
0
TCW1
TCW0
0
0
R/W
R/W
1
0
1
1
R/W
R/W
(initial value)
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