Block Diagram; Block Configuration; Figure 6.7 Block Diagram Of Flash Memory - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Section 6 ROM

Block Diagram

FLMCR1: Flash memory control register 1

FLMCR2: Flash memory control register 2

Erase block register

FLPWCR: Flash memory power control register

Flash memory enable register

Figure 6.8 shows the block configuration of flash memory. The thick lines indicate erasing units,

the narrow lines indicate programming units, and the values are addresses. The flash memory is

divided into 1 Kbyte × 4 blocks, 28 Kbytes × 1 block, 16 Kbytes × 1 block, 8 Kbytes × 1 block

and 4 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in 128-

byte units starting from an address with lower eight bits H'00 or H'80.

Rev. 6.00 Aug 04, 2006 page 168 of 680

REJ09B0145-0600

Internal address bus

Internal data bus (16 bits)

Bus interface/controller

Flash memory