Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/38024, H8/38024S, H8/38024F-ZTAT, H8/38124 Group Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series Rev. 6.00 Revision Date: Aug 27, 2004...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 4 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 5 Preface The H8/38024 Group is a single-chip microcomputer built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/38024 Group incorporates peripheral functions including ROM, RAM, timer, serial communications interface (SCI), 10-bit PWM, A/D converter, LCD controller/driver, and I/O ports. It is a microcomputer allowing the implementation of a sophisticated control system.
Page 6: Specifications
Specifications 38024 38024R 38024S 38124 Item ZTAT Mask Flash Flash Mask Flash Mask Memory 32 Kbytes 8 Kbytes 32 Kbytes 32 Kbytes 8 Kbytes 32 Kbytes 8 Kbytes 32 Kbytes 32 Kbytes 32 Kbytes 1 Kbyte 512 bytes 1 Kbyte 1 Kbyte 512 bytes 1 Kbyte...
Page 7 Purpose: This manual provides the information of the hardware functions and electrical characteristics of the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT, and H8/38124 Group. The H8/300L Series Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with this manual.
Page 8 Notes: The following limitations apply to H8/38024 and H8/38124 programming and debugging when the on-chip emulator is used. 1. Pin 95 is not available because it is used exclusively by the on-chip emulator. 2. Pins 33, 34, and 35 are unavailable for use. In order to use these pins additional hardware must be mounted on the user board.
Page 9 List of Items Revised or Added for This Version Item Page Revisions (See Manual for Details) 1.1 Overview Table 1.1 amended Table 1.1 Features Product Code ROM/RAM Size Mask ROM Version ZTAT Version F-ZTAT Version Package (Byte) HD64338024 HD64738024 HD64F38024R FP-80A 32K/1K HD64F38024...
Page 10 Wait Time Oscillation stabilization wait time = oscillation stabilization time + wait time + (8 to 16,384 states) * ....(1) (to 131,072 states) * Notes: 1. H8/38024 Group 2. H8/38124 Group 5.1 Overview Table 5.1 amended Table 5.1 Operating...
Page 11 Item Page Revisions (See Manual for Details) 8.1 Overview 187, Table 8.1 amended Table 8.1 Port Function Switching Functions Port Description Pins Other Functions Registers • Port 3 /AEVL Asynchronous counter event PMR3 8-bit I/O port /AEVH input pins AEVL, AEVH ECCR •...
Page 12 Item Page Revisions (See Manual for Details) 9.6.2 Register Timer Mode Register (TMW) Descriptions Bits 3 to 0—Clock Select (CKS3 to CKS0) Bit table amended Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Description Watchdog on-chip oscillator 9.7.2 Register Event Counter Control/Status Register (ECCSR) Configurations...
Page 13 Item Page Revisions (See Manual for Details) 14.3.2 Low-Voltage Description amended Detection Circuit 2. After waiting for LVDCNT overflow, etc., to ensure that the = 150 µs) for the reference voltage Operation and stabilization time (t LVDON Cancellation Setting and low voltage detection power supply has elapsed, clear Procedure Using LVDR bits LVDDF and LVDUF in LVDSR to 0.
Page 14 Item Page Revisions (See Manual for Details) 16.8.1 Power Supply Figure amended Voltage and Operating Ranges Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected) 0.35 • Active (high-speed) mode • Sleep (high-speed) mode 16.8.2 DC Table 16.21 amended Characteristics Values Table 16.21 DC...
Page 15 Item Page Revisions (See Manual for Details) 16.8.2 DC 497 to Table 16.21 amended, note *6 added Characteristics Values Item Symbol Applicable Pins Unit Test Condition Notes Table 16.21 DC — — µA Watch = 2.7 V, WATCH Characteristics mode = 25°C, Reference current...
Page 16 Item Page Revisions (See Manual for Details) 16.8.3 AC 500, Table 16.22 amended, note *2 added Characteristics Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Table 16.22 Control — 16.0 System clock , OSC Signal Timing oscillation — On-chip oscillator frequency selected...
Page 17 Item Page Revisions (See Manual for Details) E. List of Product Table E.1 amended Codes Package Product Type Product Code Mark Code (Package Code) Table E.1 H8/38024 H8/38124 HD64F38124H F38124H 80-pin QFP (FP-80A) H8/38124 F-ZTAT Regular Group versions specifications Group Product Code...
Page 18 Rev. 6.00, 08/04, page xviii of xxx...
Page 19: Table Of Contents
Contents Section 1 Overview ......................Overview........................... Internal Block Diagram..................... Pin Arrangement and Functions..................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions ....................... 19 Section 2 CPU ........................25 Overview........................... 25 2.1.1 Features........................ 25 2.1.2 Address Space...................... 26 2.1.3 Register Configuration..................26 Register Descriptions ......................
Page 20 Memory Map ........................59 2.8.1 Memory Map ....................... 59 Application Notes ......................64 2.9.1 Notes on Data Access ..................64 2.9.2 Notes on Bit Manipulation................... 66 2.9.3 Notes on Use of the EEPMOV Instruction ............72 Section 3 Exception Handling ..................
Page 21 Clearing Module Standby Mode ................139 Section 6 ROM ........................141 Overview........................... 141 6.1.1 Block Diagram ..................... 141 H8/38024 PROM Mode ....................142 6.2.1 Setting to PROM Mode ..................142 6.2.2 Socket Adapter Pin Arrangement and Memory Map........... 142 H8/38024 Programming....................145 6.3.1...
Page 22 Reliability of Programmed Data ..................151 Flash Memory Overview ....................152 6.5.1 Features........................ 152 6.5.2 Block Diagram..................... 153 6.5.3 Block Configuration..................... 154 6.5.4 Register Configuration..................155 Descriptions of Registers of the Flash Memory..............156 6.6.1 Flash Memory Control Register 1 (FLMCR1)............. 156 6.6.2 Flash Memory Control Register 2 (FLMCR2).............
Page 23 8.2.1 Overview......................189 8.2.2 Register Configuration and Description............... 189 8.2.3 Pin Functions ....................... 194 8.2.4 Pin States......................195 8.2.5 MOS Input Pull-Up....................195 Port 3..........................196 8.3.1 Overview......................196 8.3.2 Register Configuration and Description............... 196 8.3.3 Pin Functions ....................... 201 8.3.4 Pin States......................
Page 24 8.10 Port A..........................226 8.10.1 Overview......................226 8.10.2 Register Configuration and Description............... 226 8.10.3 Pin Functions ....................... 228 8.10.4 Pin States ......................229 8.11 Port B ..........................230 8.11.1 Overview......................230 8.11.2 Register Configuration and Description............... 230 8.11.3 Pin Functions ....................... 232 8.12 Input/Output Data Inversion Function ................
Page 25 9.6.1 Overview......................290 9.6.2 Register Descriptions ................... 293 9.6.3 Timer Operation....................299 9.6.4 Watchdog Timer Operation States ............... 300 Asynchronous Event Counter (AEC) ................301 9.7.1 Overview......................301 9.7.2 Register Configurations ..................304 9.7.3 Operation ......................313 9.7.4 Asynchronous Event Counter Operation Modes..........317 9.7.5 Application Notes ....................
Page 26 11.2.1 PWM Control Register (PWCRm) ..............380 11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm) ........382 11.2.3 Clock Stop Register 2 (CKSTPR2)..............383 11.3 Operation .......................... 384 11.3.1 Operation ......................384 11.3.2 PWM Operation Modes ..................385 Section 12 A/D Converter ....................
Page 27 15.2 When Not Using Internal Power Supply Step-Down Circuit..........440 Section 16 Electrical Characteristics ................441 16.1 H8/38024 ZTAT Version and Mask ROM Version Absolute Maximum Ratings.... 441 16.2 H8/38024 ZTAT Version and Mask ROM Version Electrical Characteristics ....442 16.2.1 Power Supply Voltage and Operating Range............442 16.2.2 DC Characteristics ....................
Page 28 16.6.1 Power Supply Voltage and Operating Range............472 16.6.2 DC Characteristics ....................474 16.6.3 AC Characteristics ....................481 16.6.4 A/D Converter Characteristics ................484 16.6.5 LCD Characteristics..................... 485 16.7 Absolute Maximum Ratings of H8/38124 Group ............. 486 16.8 Electrical Characteristics of H8/38124 Group ..............487 16.8.1 Power Supply Voltage and Operating Ranges .............
Page 29 Appendix E List of Product Codes ................. 616 Appendix F Package Dimensions ................... 619 Appendix G Specifications of Chip Form ..............623 Appendix H Form of Bonding Pads ................625 Appendix I Specifications of Chip Tray ..............626 Rev. 6.00, 08/04, page xxix of xxx...
Page 30 Rev. 6.00, 08/04, page xxx of xxx...
Page 31: Section 1 Overview
The H8/38024 is also available in a ZTAT™ * version with on-chip PROM which can be programmed as required by the user. The H8/38024 is also available in F-ZTAT™ * versions with on-chip flash memory which can be reprogrammed on board.
Page 32 Table 1.1 Features Item Specification High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed  Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S Group)  Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 µs (operating at φ = 5 MHz) ...
Page 33 Subactive mode • Active (medium-speed) mode Memory Large on-chip memory • H8/38024, H8/38024S, and H8/38124: 32-Kbyte ROM, 1-Kbyte RAM • H8/38023, H8/38023S, and H8/38123: 24-Kbyte ROM, 1-Kbyte RAM • H8/38022, H8/38022S, and H8/38122: 16-Kbyte ROM, 1-Kbyte RAM • H8/38021, H8/38021S, and H8/38121: 12-Kbyte ROM, 512 byte RAM •...
Page 34 Item Specification Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ) * and four clock signals divided from the watch clock (φ • Asynchronous event counter: 16-bit timer ...
Page 35 Item Specification • Serial SCI3: 8-bit synchronous/asynchronous serial interface communication Incorporates multiprocessor communication function interface 10-bit PWM Pulse-division PWM output for reduced ripple • Can be used as a 10-bit D/A converter by connecting to an external low- pass filter. A/D converter Successive approximations using a resistance ladder •...
Page 36 Item Specification Product lineup Product Code ROM/RAM Size Mask ROM Version ZTAT Version F-ZTAT Version Package (Byte) HD64338024 HD64738024 HD64F38024R FP-80A 32K/1K HD64F38024 FP-80B TFP-80C TLP-85V (HD64F38024R only) Die (mask ROM/F-ZTAT version only) HD64338023 — — FP-80A 24K/1K FP-80B TFP-80C HD64338022 —...
Page 37: Internal Block Diagram
Internal Block Diagram Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group. Figure 1.1(2) shows a block diagram of the H8/38124 Group. = AV Sub clock H8/300L TEST /COM /COM System clock /COM (512 bytes to 1 Kbyte)
Page 38 = AV Sub clock H8/300L TEST /COM /COM System clock /COM (512 bytes to 1 Kbyte) /COM IRQAEC /TMIG (8 Kbytes to 32 Kbytes) /IRQ /ADTRG 10-bit PWM1 /IRQ /TMIF Power-on reset and low-voltage detect circuits /PWM /PWM /TMOFL /TMOFH /SEG /SEG 10-bit PWM2...
Page 39: Pin Arrangement And Functions
1.3.1 Pin Arrangement The H8/38024 Group, H8/38024S Group, and H8/38124 Group pin arrangements are shown in figures 1.2, 1.3, and 1.4. The bonding pad location diagram of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 is shown in figure 1.5. The bonding pad coordinates of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are given in table 1.2.
Page 40 /SEG /SEG /TMOFL /SEG /TMOFH /SEG /SEG /SEG /AEVH /SEG /AEVL /SEG /SEG /SCK /SEG /RXD FP-80A,TFP-80C /TXD (Top view) /SEG /IRQ /SEG /extD /SEG /extU /SEG /SEG /SEG /IRQ /TMIC /SEG /SEG /SEG /SEG Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.2(2) Pin Arrangement (FP-80A, TFP-80C: Top View, H8/38124 Group) Rev.
Page 41 /SEG Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user. Figure 1.3 Pin Arrangement (FP-80B: Top View, H8/38024 Group, H8/38024F-ZTAT Group) Rev. 6.00, 08/04, page 11 of 628...
Page 42 TLP-85V (Top view) Note: Pins are shown in transparent view. Figure 1.4 Pin Arrangement (TLP-85V, H8/38024RF-ZTAT Group, H8/38024S Group) Rev. 6.00, 08/04, page 12 of 628...
Page 43 Type code (0, 0) Chip size: 3.99 mm × 3.99 mm Voltage level on the back of the chip: GND Figure 1.5 Bonding Pad Location Diagram of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 (Top View) Rev. 6.00, 08/04, page 13 of 628...
Page 44 Table 1.2 Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No. Pad Name Pad No.
Page 45 (0, 0) Type code 34 36 38 35 37 Chip size: 3.84 mm × 4.24 mm Voltage level on the back of the chip: GND : NC pad Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View) Rev. 6.00, 08/04, page 15 of 628...
Page 46 Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No. Pad Name Pad No. Pad Name PB7/AN7 –1802...
Page 47 (0.0) Chip size: 2.91 mm × 2.91 mm Voltage level on the back of the chip: GND Figure 1.7 Bonding Pad Location Diagram of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S (Top View) Rev. 6.00, 08/04, page 17 of 628...
Page 48 Table 1.4 Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Coordinates Coordinates X (µ µ µ µ m) Y (µ µ µ µ m) X (µ µ µ µ m) Y (µ µ µ µ m) Pad No. Pad Name Pad No.
Page 49: Pin Functions
1.3.2 Pin Functions Table 1.5 outlines the pin functions of the H8/38024 Group. Table 1.5 Pin Functions Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Power Input Power supply: All V...
Page 50 Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Clock Input These pins connect to a pins crystal or ceramic Output oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram.
Page 51 Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions Timer AEVL Input Asynchronous event pins AEVH counter event input: This is an event input pin for input to the asynchronous event counter. TMIC Input Timer C event input:...
Page 52 Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions I/O ports Port 1: This is a 4-bit I/O port. Input or output can be designated for each bit by means of port control register 1 (PCR1).
Page 53 Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions I/O ports 44 to 37 46 to 39 H9, J9 45 to 46 to 44 to Port 8: This is an 8-bit I/O H10, J10 port.
Page 54 Pin No. FP-80A No. * No. * No. * Type Symbol TFP-80C FP-80B TLP-85V Name and Functions 45 to 48 47 to 50 G10, G8 46 to 47 to 45 to Output LCD common output: controller/ G9, F10 These are the LCD driver common output pins.
Page 55: Section 2 Cpu
Section 2 CPU Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. •...
Page 56: Address Space
2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Page 57: Register Descriptions
Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Page 58 Condition Code Register (CCR) This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.
Page 59: Initial Register Values
2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized.
Page 60: Data Formats In General Registers
2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No. Data Format 1-bit data Don't care 1-bit data Don't care Byte data Don't care Byte data Don't care Word data...
Page 61: Memory Data Formats
2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed.
Page 62: Addressing Modes
Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes Address Modes Symbol Register direct Register indirect Register indirect with displacement @(d:16, Rn) Register indirect with post-increment @Rn+...
Page 63 Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand.
Page 64: Effective Address Calculation
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address.
Page 65 Table 2.2 Effective Address Calculation Rev. 6.00, 08/04, page 35 of 628...
Page 66 Rev. 6.00, 08/04, page 36 of 628...
Page 67 Rev. 6.00, 08/04, page 37 of 628...
Page 68: Instruction Set
Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Instruction Set Function Instructions Number MOV, PUSH * , POP * Data transfer Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG Logic operations AND, OR, XOR, NOT...
Page 69 Notation General register (destination) General register (source) General register (EAd), <EAd> Destination operand (EAs), <EAs> Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer #IMM...
Page 70: Data Transfer Instructions
2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Page 71 Rm→Rn @Rm←→Rn @(d:16, Rm)←→Rn disp @Rm+→Rn, or Rn →@−Rm @aa:8←→Rn @aa:16←→Rn #xx:8→Rn #xx:16→Rn PUSH, POP → @SP+ Rn, or → @−SP [Legend] Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 Data Transfer Instruction Codes Rev.
Page 72: Arithmetic Operations
2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Size * Instruction Function Rd ± Rs → Rd, Rd + #IMM → Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register.
Page 73: Logic Operations
2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Logic Operation Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data Rd ∨...
Page 74 Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT MULXU, DIVXU ADD, ADDX, SUBX, CMP (#XX:8) AND, OR, XOR (Rm) AND, OR, XOR (#xx:8) SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR [Legend]...
Page 75: Bit Manipulations
2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 76 Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. C ⊕ [~(<bit-No.> of <EAd>)] → C BIXOR XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag.
Page 77 BSET, BCLR, BNOT, BTST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: register direct (Rm) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) Operand:...
Page 78 BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register indirect (@Rn) Bit No.: immediate (#xx:3) Operand: absolute (@aa:8) Bit No.: immediate (#xx:3) [Legend] Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont) Rev.
Page 79: Branching Instructions
2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function — Branches to the designated address if condition cc is true. The branching conditions are given below. Mnemonic Description Condition...
Page 80 disp JMP (@Rm) JMP (@aa:16) JMP (@@aa:8) disp JSR (@Rm) JSR (@aa:16) JSR (@@aa:8) [Legend] Operation field Condition field Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 6.00, 08/04, page 50 of 628...
Page 81: System Control Instructions
2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Size * Instruction Function — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Page 82: Block Data Transfer Instruction
RTE, SLEEP, NOP LDC, STC (Rn) ANDC, ORC, XORC, LDC (#xx:8) [Legend] Operation field Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction Size...
Page 83 [Legend] Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 6.00, 08/04, page 53 of 628...
Page 84: Basic Operational Timing
Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φ ). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
Page 85: Access To On-Chip Peripheral Modules
2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used.
Page 86 Three-state access to on-chip peripheral modules Bus cycle state state state φ or φ Internal Address address bus Internal read signal Internal Read data data bus (read access) Internal write signal Internal data bus Write data (write access) Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) Rev.
Page 87: Cpu States
CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or medium- speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode.
Page 88: Program Execution State
Reset cleared Reset state Exception-handling state Reset occurs Reset Interrupt occurs source Reset Interrupt Exception- occurs occurs source handling occurs complete Program halt state Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Page 89: Memory Map
2.8.1 Memory Map The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and H8/38122 in figure 2.16(3), that of the H8/38021, H8/38021S, and H8/38121 in figure 2.16(4), and that of the H8/38020, H8/38020S, and H8/38120 in figure 2.16(5).
Page 90 H'0000 Interrupt vector area H'0029 H'002A 24 Kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FB80 On-chip RAM 1024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map Rev.
Page 91 H'0000 Interrupt vector area H'0029 H'002A 16 Kbytes On-chip ROM (16384 bytes) H'3FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FB80 On-chip RAM 1024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(3) H8/38022, H8/38022S, and H8/38122 Memory Map Rev.
Page 92 H'0000 Interrupt vector area H'0029 H'002A 12 Kbytes On-chip ROM (12288 bytes) H'2FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map Rev.
Page 93 H'0000 Interrupt vector area H'0029 H'002A 8 Kbytes On-chip ROM (8192 bytes) H'1FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map Rev.
Page 94: Application Notes
Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur.
Page 95 Notes: These examples apply to the H8/38024. 1. On the H8/38024, H8/38124, and H8/38024S, 32 Kbytes and the address is H'7FFF; on the H8/38023, H8/38123, and H8/38023S, 24 Kbytes and the address is H'5FFF; on the H8/38022, H8/38122, and H8/38022S, 16 Kbytes and the address is H'3FFF; on the H8/38021, H8/38121, and H8/38021S, 12 Kbytes and the address is H'2FFF;...
Page 96: Notes On Bit Manipulation
2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write- only bits, and when the instruction accesses an I/O port.
Page 97 Example 2: BSET instruction executed designating port 3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P3 to high-level output.
Page 98 [A: Prior to executing BSET] The PDR3 value (H'80) is written to a work area in memory MOV. B #80, (RAM0) as well as to PDR3 MOV. B R0L, @RAM0 MOV. B R0L, @PDR3 Input/output Input Input Output Output Output Output Output Output...
Page 99 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a high-level signal at P3 .
Page 100 [A: Prior to executing BCLR] The PCR3 value (H'3F) is written to a work area in memory MOV. B #3F, (RAM0) as well as to PCR3. MOV. B R0L, @RAM0 MOV. B R0L, @PCR3 Input/output Input Input Output Output Output Output Output Output...
Page 101 Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter C/Timer load register C TCC/TLC H'FFB5 Port data register 1 * PDR1 H'FFD4 Port data register 3 * PDR3 H'FFD6 Port data register 4 * PDR4 H'FFD7 Port data register 5 * PDR5 H'FFD8 Port data register 6 *...
Page 102: Notes On Use Of The Eepmov Instruction
2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ←...
Page 103: Section 3 Exception Handling
Section 3 Exception Handling Overview Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1...
Page 104: Interrupt Immediately After Reset
When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. See section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the H8/38124 Group, which is equipped with an on-chip power-on reset circuit. Reset cleared Program initial instruction prefetch...
Page 105: Interrupts
Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP to WKP , IRQ , IRQ , IRQ , IRQ IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Page 106 Table 3.2 Interrupt Sources and Their Priorities Interrupt Source Interrupt Vector Number Vector Address Priority Reset H'0000 to H'0001 High Watchdog timer H'0008 to H'0009 Low-voltage detect interrupt * LVDI * H'000A to H'000B IRQAEC IRQAEC H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 Timer A...
Page 107: Interrupt Control Registers
3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Interrupt Control Registers Name Abbreviation Initial Value Address IRQ edge select register IEGR — H'FFF2 Interrupt enable register 1 IENR1 — H'FFF3 Interrupt enable register 2 IENR2 —...
Page 108 Bit 3—IRQ Edge Select (IEG3) Bit 3 selects the input sensing of the IRQ pin and TMIF pin. Bit 3 IEG3 Description Falling edge of IRQ and TMIF pin input is detected (initial value) Rising edge of IRQ and TMIF pin input is detected Bit 2—Reserved Bit 2 is reserved: it can only be written with 0.
Page 109 Bit 7—Timer A Interrupt Enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests. Bit 7 IENTA Description Disables timer A interrupt requests (initial value) Enables timer A interrupt requests Bit 6—Reserved Bit 6 is reserved: it can only be written with 0. Bit 5—Wakeup Interrupt Enable (IENWP) Bit 5 enables or disables WKP to WKP...
Page 110 Bits 1 and 0—IRQ and IRQ Interrupt Enable (IEN1 and IEN0) Bits 1 and 0 enable or disable IRQ and IRQ interrupt requests. Bit n IENn Description Disables interrupt requests from pin IRQn (initial value) Enables interrupt requests from pin IRQn (n = 1 or 0) Interrupt Enable Register 2 (IENR2) IENDT...
Page 111 Bit 4—Timer G Interrupt Enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests. Bit 4 IENTG Description Disables timer G interrupt requests (initial value) Enables timer G interrupt requests Bit 3—Timer FH Interrupt Enable (IENTFH) Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Page 112 Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests. Bit 0 IENEC Description Disables asynchronous event counter interrupt requests (initial value) Enables asynchronous event counter interrupt requests For details of SCI3 interrupt control, see section 10.2.6 Serial control register 3 (SCR3). Interrupt Request Register 1 (IRR1) ...
Page 113 Bits 4 and 3—IRQ and IRQ Interrupt Request Flags (IRRI4 and IRRI3) Bit n IRRIn Description Clearing conditions: (initial value) When IRRIn = 1, it is cleared by writing 0 Setting conditions: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 4 or 3) Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Page 114 Interrupt Request Register 2 (IRR2)  IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTC IRREC  Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter interrupt is requested.
Page 115 Bit 4—Timer G Interrupt Request Flag (IRRTG) Bit 4 IRRTG Description Clearing conditions: (initial value) When IRRTG = 1, it is cleared by writing 0 Setting conditions: When the TMIG pin is designated for TMIG input and the designated signal edge is input, and when TCG overflows while OVIE is set to 1 in TMG Bit 3—Timer FH Interrupt Request Flag (IRRTFH) Bit 3...
Page 116 Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC) Bit 0 IRREC Description Clearing conditions: (initial value) When IRREC = 1, it is cleared by writing 0 Setting conditions: When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit counter mode Wakeup Interrupt Request Register (IWPR) IWPF7...
Page 117: External Interrupts
Wakeup Edge Select Register (WEGR) WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. WKPn Edge Select (WKEGSn) Bit n—WKP Bit n selects WKPn pin input sensing.
Page 118: Internal Interrupts
Interrupts IRQ , IRQ , IRQ and IRQ Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ , IRQ , IRQ and IRQ . These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
Page 119: Interrupt Operations
3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Interrupt request External interrupts or internal interrupt enable...
Page 120 • The I bit of CCR is set to 1, masking further interrupts. • The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed.
Page 121 Program execution state IRRI0 = 1 IEN0 = 1 IRRI1 = 1 IEN1 = 1 IRREC2 = 1 IENEC2 = 1 IRRDT = 1 IENDT = 1 I = 0 PC contents saved CCR contents saved I ← 1 Branch to interrupt handling routine [Legend] Program counter...
Page 122 SP − 4 SP (R7) SP − 3 SP + 1 SP − 2 SP + 2 SP − 1 SP + 3 SP (R7) SP + 4 Even address Stack area Prior to start of interrupt After completion of interrupt PC and CCR exception handling exception handling...
Page 123 Figure 3.5 Interrupt Sequence Rev. 6.00, 08/04, page 93 of 628...
Page 124: Interrupt Response Time
3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction * 1 to 13 15 to 27 Saving of PC and CCR to stack...
Page 125: Application Notes
Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address.
Page 126: Notes On Rewriting Port Mode Registers
3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of IRQAEC, the following points should be observed. When an external interrupt pin function is switched by rewriting the port mode register that controls pins IRQ , IRQ...
Page 127 Interrupt Request Flags Set to 1 Conditions When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP IWPR IWPF7 is low and WEGR bit WKEGS7 = 0. When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP is low and WEGR bit WKEGS7 = 1.
Page 128: Method For Clearing Interrupt Request Flags
An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and determining its value is complicated.
Page 129 MOV.B @IRR1:8,R1L ..IRRI0 = 0 at this time AND.B #B'11111101,R1L ..Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 ..IRRI0 is cleared to 0 In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B instruction is executing.
Page 130 Rev. 6.00, 08/04, page 100 of 628...
Page 131: Section 4 Clock Pulse Generators
In the H8/38124 Group, the system clock pulse generator includes an on-chip oscillator. 4.1.1 Block Diagram Figure 4.1 shows a block diagram of the clock pulse generators of the H8/38024, H8/38024S, and H8/38024F-ZTAT Group. Figure 4.2 shows a block diagram of the clock pulse generators of the H8/38124 Group.
Page 132: System Clock And Subclock
Internal reset signal (other than watchdog timer or low-voltage detect circuit reset) IRQAEC Latch φ System System φ clock φ clock φ System divider oscillator φ clock (1/2) φ /2 φ divider Prescaler S φ /128 (13 bits) φ /8192 On-chip oscillator System clock pulse generator...
Page 133 Clock Pulse Generator Control Register (OSCCR) SUBSTP — — — — IRQAECF OSCF — Initial value — — Read/Write OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets, and controls whether the subclock oscillator operates or not.
Page 134: System Clock Generator
On-Chip Oscillator Selection Method, for information on selecting the on-chip oscillator. Connecting a Crystal Oscillator Figure 4.3(1) shows a typical method of connecting a crystal oscillator to the H8/38024 or H8/38024F-ZTAT Group, and figure 4.3(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group.
Page 135 Ω ±20% R = 1 M Crystal Products Frequency Recommendation oscillator name value 12 pF ±20% 4.0 MHz NR-18 Note: Circuit constants should be determined in consultation with the resonator manufacturer. Figure 4.3(2) Typical Connection to Crystal Oscillator (H8/38024S, H8/38124 Group) Figure 4.3 shows the equivalent circuit of a crystal oscillator.
Page 136 Connecting a Ceramic Oscillator Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or H8/38024F-ZTAT Group, and figure 4.5(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group. Ω...
Page 137 To be avoided Signal A Signal B Figure 4.6 Board Design of Oscillator Circuit Note: The circuit parameters above are recommended by the crystal or ceramic oscillator manufacturer. The circuit parameters are affected by the crystal or ceramic oscillator and floating capacitance when designing the board.
Page 138 On-Chip Oscillator Selection Method (H8/38124 Group Only) The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3 lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC pin input level set during resets must be fixed at V or GND, based on the oscillator to be selected.
Page 139: Subclock Generator
Subclock Generator Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. notes on board design for the system clock in section 4.2.
Page 140 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X to GND and leave pin X open, as shown in figure 4.10. Open Figure 4.10 Pin Connection when not Using Subclock External Clock Input Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.11. Note that no external clock should be input to the H8/38124 Group.
Page 141: Prescalers
Prescalers The H8/38024 Group is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Page 142: Note On Oscillators
Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors.
Page 143: Definition Of Oscillation Stabilization Wait Time
Modification point OSC1 OSC1 OSC2 OSC2 Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 Modification point Modification point OSC1 OSC1 OSC2 OSC2 (3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3 Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.1 Definition of Oscillation Stabilization Wait Time...
Page 144 1. Oscillation stabilization time (t The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Wait time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized.
Page 145: Notes On Use Of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
+ (8 to 16,384 states) * ....(1) (up to 131,072 states) * Notes: 1. H8/38024 Group 2. H8/38124 Group Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock oscillator, careful evaluation must be carried out on the installation circuit before deciding on the oscillation stabilization wait time.
Page 146: Note On Use Of Hd64F38024
Note: * This figure applies to the H8/38024, H8/38024S, and H8/38024F-ZTAT Groups. The number of states on the H8/38124 Group is 8,192 or more. 4.5.3 Note on Use of HD64F38024 When using the HD64F38024, the oscillators may not operate if an initial voltage of 10 mV is applied to the V pin during power-on.
Page 147: Section 5 Power-Down Modes
Section 5 Power-Down Modes Overview The LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes. Table 5.1 Operating Modes Operating Mode Description Active (high-speed) mode...
Page 148 Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode. Program Program Reset state execution state halt state SLEEP instruction Active Sleep (high-speed) (high-speed) Program mode mode halt state Standby mode SLEEP instruction Active Sleep...
Page 149 On the H8/38124 Group, operates when φ /32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, operates when φ is selected as the internal clock; otherwise stops and stands by.
Page 150: System Control Registers
/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, stops and stands by. 11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, stops and stands by.
Page 151 Note that stabilization times for the H8/38024, H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different.
Page 152 Bit 3—Low Speed on Flag (LSON) This bit chooses the system clock (φ) or subclock (φ ) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON Description...
Page 153 Bit 4—Noise Elimination Sampling Frequency Select (NESEL) This bit selects the frequency at which the watch clock signal (φ ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (φ ) generated by the system clock pulse generator.
Page 154: Sleep Mode
Bit 2—Medium Speed on Flag (MSON) After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. Bit 2 MSON Description Operation in active (high-speed) mode (initial value) Operation in active (medium-speed) mode Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0) /2, φ...
Page 155: Clearing Sleep Mode
5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, IRQAEC, IRQ , IRQ , IRQ , IRQ , WKP to WKP , SCI3, A/D converter), or by input at the RES pin.
Page 156: Standby Mode
Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Page 157: Oscillator Stabilization Time After Standby Mode Is Cleared
Oscillator Stabilization Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different. • When a oscillator is used The table below gives settings for various operating frequencies.
Page 158: Standby Mode Transition And Pin States
• When an external clock is used STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU sometimes will start operation before wait time completion. • When the on-chip oscillator is used 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group.
Page 159: Notes On External Input Signal Changes Before/After Standby Mode
5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ or subclock φ (referred to together in this section as the internal clock).
Page 160 Active (high-speed, Wait for Active (high-speed, Operating medium-speed) mode Standby mode oscillation medium-speed) mode mode or subactive mode or watch mode to settle or subactive mode subcyc subcyc subcyc subcyc φ or φ External input signal Capture possible: case 1 Capture possible: case 2 Capture possible:...
Page 161: Watch Mode
Watch Mode 5.4.1 Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F, timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
Page 162: Subsleep Mode
Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1.
Page 163: Subactive Mode
Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ , or WKP interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter, SCI3, IRQAEC, IRQ , IRQ...
Page 164: Active (Medium-Speed) Mode
Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ , IRQ or WKP to WKP interrupts in standby...
Page 165: Direct Transfer
Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1.
Page 166: Direct Transition Times
• Direct transfer from subactive mode to active (medium-speed) mode When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed.
Page 167 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Page 168: Notes On External Input Signal Changes Before/After Direct Transition
4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Page 169: Module Standby Mode
Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode.
Page 170 Register Name Bit Name Operation CKSTPR2 LDCKSTP LCD module standby mode is cleared LCD is set to module standby mode PW1CKSTP PWM1 module standby mode is cleared PWM1 is set to module standby mode WDCKSTP Watchdog timer module standby mode is cleared Watchdog timer is set to module standby mode AECKSTP Asynchronous event counter module standby mode...
Page 171: Section 6 Rom
H8/38120 have 8 Kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. The H8/38024 has a ZTAT version and F-ZTAT version with 32-Kbyte PROM and flash memory. A F-ZTAT™ version of the H8/38124 is available, and it has 32 Kbytes of flash memory.
Page 172: H8/38024 Prom Mode
H8/38024 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set the chip to PROM mode.
Page 173 H8/38024 EPROM socket FP-80A, TFP-80C FP-80B HN27C101 (32-pin) TEST = AV Note: Pins not indicated in the figure should be left open. Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101) Rev. 6.00, 08/04, page 143 of 628...
Page 174 H'8000 onward, it may not be possible to continue PROM programming and verification. When programming, H'FF should be set as the data in this address area (H'8000 to H'1FFFF). Figure 6.3 H8/38024 Memory Map in PROM Mode Rev. 6.00, 08/04, page 144 of 628...
Page 175: H8/38024 Programming
H8/38024 Programming The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode. Table 6.2 Mode Selection in PROM Mode (H8/38024) Pins Mode to EO to EA Write Data input Address input Verify Data output...
Page 176 Start Set write/verify mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V Address = 0 n = 0 → n + 1 n < 25 = 0.2 ms ± 5% Write time t → Address + 1 address Verify Write time t...
Page 177 Tables 6.3 and 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C Test Item Symbol Min Unit Condition Input high-level...
Page 178 Table 6.4 AC Characteristics Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C Item Symbol Unit Test Condition Figure 6.5 * Address setup time — — µs OE setup time — — µs Data setup time —...
Page 179 Figure 6.5 shows a PROM write/verify timing diagram. Write Verify Address Data Input data Output data CC +1 Note: * t is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6.5 PROM Write/Verify Timing Rev. 6.00, 08/04, page 149 of 628...
Page 180: Programming Precautions
) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas (former Hitachi) specifications for the HN27C101 will result in correct V of 12.5 V.
Page 181: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is in use, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 182: Flash Memory Overview
Flash Memory Overview 6.5.1 Features The features of the 32-Kbyte flash memory built into HD64F38024, HD64F38024R, and HD64F38124 are summarized below. • Programming/erase methods  The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Page 183: Block Diagram
6.5.2 Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 TES pin FLMCR2 Operating Bus interface/controller P95 pin mode P34 pin FLPWCR FENR Flash memory (32 Kbytes) [Legend] FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR: Erase block register FLPWCR: Flash memory power control register...
Page 184: Block Configuration
6.5.3 Block Configuration Figure 6.8 shows the block configuration of 32-Kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes × 1 block. Erasing is performed in these units.
Page 185: Register Configuration
6.5.4 Register Configuration Table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.5 Register Configuration Register Name Abbreviation Initial Value Address Flash memory control register 1 FLMCR1 H'00 H'F020 Flash memory control register 2 FLMCR2 H'00...
Page 186: Descriptions Of Registers Of The Flash Memory
Descriptions of Registers of the Flash Memory 6.6.1 Flash Memory Control Register 1 (FLMCR1) — Initial value Read/Write — FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash Memory Programming/Erasing.
Page 187 Bit 4—Program Setup (PSU) This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1 in FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time). Bit 4 Description The program setup state is cancelled...
Page 188: Flash Memory Control Register 2 (Flmcr2)
Bit 0—Program (P) This bit is to set changing to or cancelling program mode (do not set SWE, ESU, PSU, EV, PV, and E bits at the same time). Bit 0 Description Program mode is cancelled (initial value) When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory changes to program mode.
Page 189: Erase Block Register (Ebr)
6.6.3 Erase Block Register (EBR) — — — Initial value Read/Write — — — EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0.
Page 190: Flash Memory Enable Register (Fenr)
Bit 7 PDWND Description When this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) When this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode.
Page 191: On-Board Programming Modes
On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Page 192: Boot Mode
6.7.1 Boot Mode Table 6.8 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 6.8, Flash Memory Programming/Erasing.
Page 193 Table 6.8 Boot Mode Operation Host Operation LSI Operation Processing Contents Processing Contents Item Branches to boot program at reset-start. Bit rate Continuously transmits data H'00 at · Measures low-level period of receive data H'00. adjustment specified bit rate. · Calculates bit rate and sets it in BRR of SCI3. ·...
Page 194: Programming/Erasing In User Program Mode
6.7.2 Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Page 195: Notes On On-Board Programming
6.7.3 Notes on On-Board Programming 1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash memory. See section 4.2, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator.
Page 196 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80.
Page 197 Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 µs Set PSU bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait 50 µs n = 1 Set P bit in FLMCR1 m = 0 Wait (Wait time = programming time)
Page 198 Table 6.10 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments Programming completed Reprogram bit — Remains in erased state Table 6.11 Additional-Program Data Computation Table Additional-Program Reprogram Data Verify Data Data Comments Additional-program bit No additional programming No additional programming No additional programming Table 6.12 Programming Time...
Page 199: Erase/Erase-Verify
6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR).
Page 200 Erase start SWE bit ← 1 Wait 1 µs n ← 1 Set EBR Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 Wait 10 µs Disable WDT EV bit ←...
Page 201: Program/Erase Protection
Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode.
Page 202: Programmer Mode
Use a PROM programmer that supports the MCU device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory (F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer mode, see table 6.7.
Page 203 HD64F38024, HD64F38024R Socket Adapter HN28F101 (32 Pins) (Conversion to Pin No. 32-Pin Pin Name FP-80A Pin Name Pin No. FP-80B Arrangement) TFP-80C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 AVcc TEST [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input Chip enable...
Page 204 HD64F38124 Socket Adapter (Conversion to (32 Pins) HN28F101 Pin No. 32-Pin Pin Name FP-80A Arrangement) Pin Name Pin No. TFP-80C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 AVcc TEST [Legend] FWE: Flash-write enable I/O7 to I/O0: Data input/output A16 to A0: Address input Chip enable 4, 59...
Page 205: Memory Read Mode
6.10.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed.
Page 206 Table 6.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs Figure 6.14 nxtc CE hold time —...
Page 207 Table 6.16 AC Characteristics in Memory Read Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Access time — µs Figure 6.15 CE output delay time — Figure 6.16 OE output delay time —...
Page 208: Auto-Program Mode
6.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before auto- programming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers.
Page 209 Table 6.17 AC Characteristics in Auto-Program Mode Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C Item Symbol Unit Notes Command write cycle — µs Figure 6.17 nxtc CE hold time — CE setup time —...
Page 210: Auto-Erase Mode
6.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4.
Page 211: Status Read Mode
A15−A0 nxtc nxtc ests erase I/O7 Erase end decision signal I/O6 Erase normal decision signal I/O5−I/O0 H'20 H'20 H'00 Figure 6.18 Auto-Erase Mode Timing Waveforms 6.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 212 A15−A0 nxtc nxtc nxtc I/O7−/O0 H'71 H'71 Note: I/O2 and I/O3 are undefined. Figure 6.19 Status Read Mode Timing Waveforms Table 6.20 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 1: Abnormal end 0: Normal end I/O6 1: Command error 0: Otherwise I/O5...
Page 213: Status Polling
6.10.7 Status Polling 1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. Table 6.21 Status Polling Output Truth Table I/O7 I/O6 I/O0 to 5 Status During internal operation...
Page 214: Notes On Memory Programming
2. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 215: Section 7 Ram
Section 7 RAM Overview The H8/38024, H8/38023, H8/38022, H8/38124, H8/38123, H8/38122, H8/38024S, H8/38023S, and H8/38022S have 1 Kbyte of high-speed static RAM on-chip, and the H8/38021, H8/38020, H8/38121, H8/38120, H8/38021S, and H8/38020S have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
Page 216 Rev. 6.00, 08/04, page 186 of 628...
Page 217: Section 8 I/O Ports
Section 8 I/O Ports Overview The LSI is provided with five 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data.
Page 218 Function Switching Port Description Pins Other Functions Registers • Port 4 /IRQ External interrupt 0 PMR2 1-bit input port • /TXD SCI3 data output (TXD SCR3 3-bit I/O port /RXD data input (RXD ), clock SMR3 /SCK input/output (SCK SPCR •...
Page 219: Port 1
Port 1 8.2.1 Overview Port 1 is a 4-bit I/O port. Figure 8.1 shows its pin configuration. /IRQ /TMIF Port 1 /IRQ /ADTRG /TMIG Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group. Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration.
Page 220 Port Data Register 1 (PDR1) — — — — Initial value — — — — Read/Write — — — — PDR1 is an 8-bit register that stores data for port 1 pins P1 , P1 *, P1 , and P1 .
Page 221 Port Pull-Up Control Register 1 (PUCR1) PUCR1 PUCR1 — PUCR1 PUCR1 — — — Initial value — — — — Read/Write PUCR1 controls whether the MOS pull-up of each of the port 1 pins P1 , P1 *, P1 , and P1 is on or off.
Page 222 ADTRG Pin Function Switch (IRQ4) ADTRG ADTRG Bit 4—P1 /IRQ /ADTRG or as IRQ This bit selects whether pin P1 /IRQ /ADTRG is used as P1 /ADTRG. Bit 4 IRQ4 Description Functions as P1 I/O pin (initial value) Functions as IRQ /ADTRG input pin Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External Trigger Input.
Page 223 Bit 2—Watchdog Timer Source Clock (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different. • H8/38024, H8/38024S, H8/38024F-ZTAT Group Bit 2 WDCKS Description Selects φ/8192...
Page 224: Pin Functions
8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Functions and Selection Method /IRQ /TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 in PCR1.
Page 225: Pin States
8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ /TMIF High- Retains Retains High- Retains Functional Functional impedance * impedance previous previous...
Page 226: Port 3
Port 3 8.3.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.2. P3 /AEVL P3 /AEVH Port 3 P3 /TMOFH P3 /TMOFL P3 /UD Figure 8.2 Port 3 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 3 register configuration.
Page 227 Port Data Register 3 (PDR3) Initial value Read/Write PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Page 228 Port Mode Register 2 (PMR2) — — POF1 — — WDCKS IRQ0 Initial value Read/Write — — — — PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P3 is on or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and switching of the P4 /IRQ pin functions.
Page 229 Port Mode Register 3 (PMR3)    AEVL AEVH TMOFH TMOFL    Initial value Read/Write PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Bit 7—P3 /AEVL Pin Function Switch (AEVL) This bit selects whether pin P3 /AEVL is used as P3 or as AEVL.
Page 230 Bit 1—P3 /TMOFL Pin Function Switch (TMOFL) This bit selects whether pin P3 /TMOFL is used as P3 or as TMOFL. Bit 1 TMOFL Description Functions as P3 I/O pin (initial value) Functions as TMOFL output pin Bit 0—P3 /UD Pin Function Switch (UD) This bit selects whether pin P3 /UD is used as P3 or as UD.
Page 231: Pin Functions
8.3.3 Pin Functions Table 8.6 shows the port 3 pin functions. Table 8.6 Port 3 Pin Functions Pin Functions and Selection Method /AEVL The pin function depends on bit AEVL in PMR3 and bit PCR3 in PCR3. AEVL PCR3 Pin function input pin output pin AEVL input pin...
Page 232: Pin States
8.3.4 Pin States Table 8.7 shows the port 3 pin states in each operating mode. Table 8.7 Port 3 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /AEVL High- Retains Retains High- Retains Functional Functional impedance * /AEVH impedance previous previous...
Page 233: Port 4
Port 4 8.4.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3. /IRQ /TXD Port 4 /RXD /SCK Figure 8.3 Port 4 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 4 register configuration. Table 8.8 Port 4 Registers Name...
Page 234 Port Control Register 4 (PCR4)      PCR4 PCR4 PCR4 Initial value      Read/Write PCR4 is an 8-bit register for controlling whether each of port 4 pins P4 to P4 functions as an input pin or output pin.
Page 235: Pin Functions
8.4.3 Pin Functions Table 8.9 shows the port 4 pin functions. Table 8.9 Port 4 Pin Functions Pin Functions and Selection Method /IRQ The pin function depends on bit IRQ0 in PMR2. IRQ0 Pin function input pin input pin /TXD The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit PCR4 in PCR4.
Page 236: Pin States
8.4.4 Pin States Table 8.10 shows the port 4 pin states in each operating mode. Table 8.10 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /IRQ High- Retains Retains High- Retains Functional Functional /TXD impedance previous previous impedance previous...
Page 237: Port 5
Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.4. /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Port 5 /WKP /SEG /WKP /SEG /WKP /SEG /WKP /SEG Figure 8.4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration.
Page 238 Port Data Register 5 (PDR5) Initial value Read/Write PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Page 239 Port Mode Register 5 (PMR5) Initial value Read/Write PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n—P5 /WKP /SEG Pin Function Switch (WKPn) When pin P5n/WKPn/SEGn+1 is not used as SEG , these bits select whether the pin is used as P5n or WKP Bit n...
Page 240: Pin Functions
8.5.3 Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Functions and Selection Method /WKP The pin function depends on bits WKP to WKP in PMR5, bits PCR5 to PCR5 in PCR5, and bits SGS3 to SGS0 in LPCR. /WKP to P5 (n = 7 to 4)
Page 241: Pin States
8.5.4 Pin States Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /WKP High- Retains Retains High- Retains Functional Functional impedance * to P5 impedance previous previous...
Page 242: Port 6
Port 6 8.6.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5. /SEG /SEG /SEG /SEG Port 6 /SEG /SEG /SEG /SEG Figure 8.5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 6 register configuration.
Page 243 Port Data Register 6 (PDR6) Initial value Read/Write PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states.
Page 244: Pin Functions
Port Pull-Up Control Register 6 (PUCR6) PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 PUCR6 Initial value Read/Write PUCR6 controls whether the MOS pull-up of each of the port 6 pins P6 to P6 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Page 245: Pin States
8.6.4 Pin States Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States Reset Sleep Subsleep Standby Watch Subactive Active /SEG High- Retains Retains High- Retains Functional Functional impedance * /SEG impedance previous previous previous...
Page 246: Port 7
Port 7 8.7.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.6. /SEG /SEG /SEG /SEG Port 7 /SEG /SEG /SEG /SEG Figure 8.6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 7 register configuration. Table 8.17 Port 7 Registers Name Abbr.
Page 247 Port Data Register 7 (PDR7) Initial value Read/Write PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Page 248: Pin Functions
8.7.3 Pin Functions Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bits PCR7 to PCR7 in PCR7 and bits SGS3 to /SEG SGS0 in LPCR. to P7 (n = 7 to 4) SGS3 to SGS0...
Page 249: Port 8
Port 8 8.8.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.7. /SEG /SEG /SEG /SEG Port 8 /SEG /SEG /SEG /SEG Figure 8.7 Port 8 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers Name Abbr.
Page 250 Port Data Register 8 (PDR8) Initial value Read/Write PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Page 251: Pin Functions
8.8.3 Pin Functions Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Functions and Selection Method /SEG The pin function depends on bits PCR8 to PCR8 in PCR8 and bits SGS3 to SGS0 in LPCR. /SEG to P8 (n = 7 to 4)
Page 252: Port 9
Port 9 8.9.1 Overview Port 9 is a 6-bit output port, configured as shown in figure 8.8. Port 9 /PWM /PWM Note: * The V pin is implemented on the H8/38124 Group only. Figure 8.8 Port 9 Pin Configuration 8.9.2 Register Configuration and Description Table 8.23 shows the port 9 register configuration.
Page 253 (initial value) Large-current port step-up circuit is turned off Note: In the H8/38024 ZTAT version and mask ROM version, and the HD64F38024R, the following precautions should be followed when accessing the PIOFF bit. When turning the voltage boost circuit on or off, always write to the register when the buffer NMOS is off (port data set to 1).
Page 254 (3) Using Port 9 with PIOFF Always Cleared to 0 This case applies to instances in which the voltage boost circuit is used constantly to generate a large current glow, or an increase in current consumption due to the operation of the voltage boost circuit is permissible even in the standby mode or watch mode (see (2) above).
Page 255: Pin Functions
Bits 1 and 0—P9 n /PWM Pin Function Switches These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1. Bit n WKPn+1 Description Functions as P9 output pin (initial value) Functions as PWM output pin (n = 0 or 1) 8.9.3 Pin Functions Table 8.24 shows the port 9 pin functions.
Page 256: Overview
8.10 Port A 8.10.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8.9. /COM /COM Port A /COM /COM Figure 8.9 Port A Pin Configuration 8.10.2 Register Configuration and Description Table 8.26 shows the port A register configuration. Table 8.26 Port A Registers Name Abbr.
Page 257 Port Control Register A (PCRA)     PCRA PCRA PCRA PCRA Initial value     Read/Write PCRA controls whether each of port A pins PA to PA functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 258: Pin Functions
8.10.3 Pin Functions Table 8.27 shows the port A pin functions. Table 8.27 Port A Pin Functions Pin Functions and Selection Method /COM The pin function depends on bit PCRA in PCRA and bits SGS3 to SGS0. SGS3 to SGS0 0000 0000 Not 0000...
Page 259: Pin States
8.10.4 Pin States Table 8.28 shows the port A pin states in each operating mode. Table 8.28 Port A Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active /COM High- Retains Retains High- Retains Functional Functional /COM impedance previous previous impedance previous...
Page 260: Overview
8.11 Port B 8.11.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8.10. Port B /IRQ /TMIC /extU * /extD * Note: * The extU and extD pins are implemented on the H8/38124 Group only. Figure 8.10 Port B Pin Configuration 8.11.2 Register Configuration and Description...
Page 261 Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. Port Mode Register B (PMRB) ...
Page 262: Pin Functions
8.11.3 Pin Functions Table 8.30 shows the port B pin functions. Table 8.30 Port B Pin Functions Pin Functions and Selection Method The pin function depends on bits CH3 to CH0 in AMR. CH3 to CH0 Not 1011 1011 Pin function input pin input pin The pin function depends on bits CH3 to CH0 in AMR.
Page 263: Input/Output Data Inversion Function
Pin Functions and Selection Method /extU Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as shown below. Note that VINTUSEL is implemented on the H8/38124 Group only. VINTUSEL CH3 to CH0 Not B'0101 B'0101 Pin function input pin input pin...
Page 264: Register Configuration And Descriptions
8.12.2 Register Configuration and Descriptions Table 8.31 shows the registers used by the input/output data inversion function. Table 8.31 Register Configuration Name Abbr. Address Serial port control register SPCR H'FF91 Serial Port Control Register (SPCR)      SPC32 SCINV3 SCINV2...
Page 265: Note On Modification Of Serial Port Control Register
Bit 3—TXD Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD pin output data is to be inverted. Bit 3 SCINV3 Description output data is not inverted (initial value) output data is inverted Bit 2—RXD Pin Input Data Inversion Switch Bit 2 specifies whether or not RXD pin input data is to be inverted.
Page 266: Application Note
8.13 Application Note 8.13.1 The Management of the Un-Use Terminal If an I/O pin not used by the user system is floating, pull it up or down. • If an unused pin is an input pin, handle it in one of the following ways: ...
Page 267: Section 9 Timers
Input capture function • Built-in capture Interval function input signal noise canceler • φ/8192 Watchdog Reset signal generated — — H8/38024, φ timer * H8/38024S, when 8-bit counter overflows H8/38024F- ZTAT Group φ/64 to φ/8192 H8/38124 Group φ oscillator On-chip...
Page 268: Timer A
• Can count asynchronous events (rising/falling/both edges) independ-ently of the MCU's internal clock Note: * The watchdog timer functions differently on the H8/38024, H8/38024S, H8/38024F-ZTAT Group and H8/38124 Group. See section 9.6, Watchdog Timer, for details. Timer A 9.2.1 Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions.
Page 269 Block Diagram Figure 9.1 shows a block diagram of timer A. φ φ φ /128 φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8 φ IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS:...
Page 270: Register Descriptions
Register Configuration Table 9.2 shows the register configuration of timer A. Table 9.2 Timer A Registers Name Abbr. Initial Value Address Timer mode register A — H'FFB0 Timer counter A H'00 H'FFB1 Clock stop register 1 CKSTPR1 H'FF H'FFFA 9.2.2 Register Descriptions Timer Mode Register A (TMA) ...
Page 271 Bits 3 to 0—Internal Clock Select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 Bit 2 Bit 1 Bit 0 Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period...
Page 272 Timer Counter A (TCA) TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA).
Page 273: Timer Operation
9.2.3 Timer Operation Interval Timer Operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately.
Page 274: Application Note
9.2.5 Application Note When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of the timer mode register A (TMA) cannot be rewritten. Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3) of the timer mode register A (TMA).
Page 275 Block Diagram Figure 9.2 shows a block diagram of timer C. φ TMIC φ IRRTC [Legend] TMC: Timer mode register C TCC: Timer counter C TLC: Timer load register C IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer C Pin Configuration Table 9.4 shows the timer C pin configuration.
Page 276: Register Descriptions
Register Configuration Table 9.5 shows the register configuration of timer C. Table 9.5 Timer C Registers Name Abbr. Initial Value Address Timer mode register C H'18 H'FFB4 Timer counter C H'00 H'FFB5 Timer load register C H'00 H'FFB5 Clock stop register 1 CKSTPR1 H'FF H'FFFA...
Page 277 Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter. Bit 6 Bit 5 TMC6 TMC5 Description TCC is an up-counter (initial value) TCC is a down-counter Hardware control by UD pin input...
Page 278 Timer Counter C (TCC) TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC).
Page 279: Timer Operation
Clock Stop Register 1 (CKSTPR1) Bit:   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value:   Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules.
Page 280 Auto-Reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count.
Page 281: Timer C Operation States
9.3.4 Timer C Operation States Table 9.6 summarizes the timer C operation states. Table 9.6 Timer C Operation States Sub- Sub- Module Operation Mode Reset Active Sleep Watch active sleep Standby Standby Interval Reset Functions Functions Halted Functions/ Functions/ Halted Halted Halted * Halted *...
Page 282: Timer F
Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL).
Page 283 Block Diagram Figure 9.3 shows a block diagram of timer F. φ IRRTFL TCRF φ TCFL TMIF Toggle Comparator TMOFL circuit OCRFL TCFH Toggle TMOFH Match Comparator circuit OCRFH TCSRF IRRTFH [Legend] TCRF: Timer control register F TCSRF: Timer control/status register F TCFH: 8-bit timer counter FH TCFL:...
Page 284 Pin Configuration Table 9.7 shows the timer F pin configuration. Table 9.7 Pin Configuration Name Abbr. Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output...
Page 285: Register Descriptions
9.4.2 Register Descriptions 16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) Bit: Initial value: Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Page 286 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) OCRF Bit: Initial value: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Read/Write: OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
Page 287 Timer Control Register F (TCRF) Bit: TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: Read/Write: TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins.
Page 288 Bit 3—Toggle Output Level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description Low level (initial value) High level Bits 2 to 0—Clock Select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Page 289 Timer Control/Status Register F (TCSRF) Bit: OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: R/(W) * R/(W) * R/(W) * R/(W) * Read/Write: Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Page 290 Bit 5—Timer Overflow Interrupt Enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description TCFH overflow interrupt request is disabled (initial value) TCFH overflow interrupt request is enabled Bit 4—Counter Clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
Page 291 Bit 2—Compare Match Flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2 CMFL Description Clearing condition: (initial value) After reading CMFL = 1, cleared by writing 0 to CMFL Setting condition:...
Page 292: Cpu Interface
Clock Stop Register 1 (CKSTPR1) Bit:   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value:   Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules.
Page 293 Figure 9.4 shows an example in which H'AA55 is written to TCF. Write to upper byte Module data bus interface (H'AA) TEMP (H'AA) TCFH TCFL Write to lower byte Module data bus interface (H'55) TEMP (H'AA) TCFH TCFL (H'AA) (H'55) Figure 9.4 Write Access to TCF (CPU →...
Page 294 Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU.
Page 295: Operation
9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers.
Page 296 TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b.
Page 297 TCF Clear Timing TCF can be cleared by a compare match with OCRF. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value).
Page 298: Application Notes
9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Page 299 If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point. As the compare match signal is output in synchronization with the TCFL clock, a compare match will not result in compare match signal generation if the clock is stopped.
Page 300 2. After program process returned normal handling, clear interrupt request flags (IRRTFH, IRRTFL) after more than that calculated with (1) formula. 3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH, OVFL) and compare match flags (CMFH, CMFL). 4.
Page 301: Timer G
Timer G 9.5.1 Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle.
Page 302 Block Diagram Figure 9.8 shows a block diagram of timer G. φ Level detector φ ICRGF Noise Edge TMIG canceler detector ICRGR IRRTG [Legend] TMG: Timer mode register G TCG: Timer counter G ICRGF: Input capture register GF ICRGR: Input capture register GR IRRTG: Timer G interrupt request flag NCS:...
Page 303: Register Descriptions
Pin Configuration Table 9.10 shows the timer G pin configuration. Table 9.10 Pin Configuration Name Abbr. Function Input capture input TMIG Input Input capture input pin Register Configuration Table 9.11 shows the register configuration of timer G. Table 9.11 Timer G Registers Name Abbr.
Page 304 TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset. Note: * An input capture signal may be generated when TMIG is modified. Input Capture Register GF (ICRGF) Bit: ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0...
Page 305 Timer Mode Register G (TMG) Bit: OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value: R/(W) * R/(W) * Read/Write: Note: * Bits 7 and 6 can only be written with 0, for flag clearing. TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock sources, counter clear selection, and edge selection for the input capture input signal interrupt request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
Page 306 Bit 5—Timer Overflow Interrupt Enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description TCG overflow interrupt request is disabled (initial value) TCG overflow interrupt request is enabled Bit 4—Input Capture Interrupt Edge Select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request.
Page 307 Clock Stop Register 1 (CKSTPR1) Bit:   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value:   Read/Write: CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer G is described here. For details of the other bits, see the sections on the relevant modules.
Page 308: Noise Canceler
9.5.3 Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS * in PMR2. Figure 9.9 shows a block diagram of the noise canceler. Sampling clock Input capture...
Page 309 Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9.10 Noise Canceler Timing (Example) Rev. 6.00, 08/04, page 279 of 628...
Page 310: Operation
9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. Timer G Functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a.
Page 311 in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see section 3.3, Interrupts. Count Timing TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four internal clock sources (φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch clock (φw).
Page 312 Figure 9.12 shows the timing in this case. Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function) Timing of Input Capture by Input Capture Input Figure 9.13 shows the timing of input capture by input capture input Input capture signal Input capture...
Page 313 TCG Clear Timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9.14 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R H'00...
Page 314: Application Notes
Timer G Operation Modes Timer G operation modes are shown in table 9.12. Table 9.12 Timer G Operation Modes Module Operation Mode Reset Active Sleep Watch Subactive Subsleep Standby Standby Input capture Reset Functions * Functions * Functions/ Functions/ Functions/ Halted Halted halted *...
Page 315 Table 9.13 Internal Clock Switching and TCG Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from low level to low level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Goes from low level to high level Clock before switching...
Page 316 Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation Goes from high level to high level Clock before switching Clock after switching Count clock Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented. Notes on Port Mode Register Modification The following points should be noted when a port mode register is modified to switch the input capture function or the input capture input noise canceler function.
Page 317 • Switching input capture input noise canceler function When performing noise canceler function switching by modifying NCS in port mode register 2 (PMR2), which controls the input capture input noise canceler, TMIG should first be cleared to 0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been input at the pin even though no valid edge has actually been input.
Page 318 When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Page 319: Timer G Application Example
9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 9.16 shows an example of the operation in this case.
Page 320: Watchdog Timer
ZTAT Group and for the H8/38124 Group are different. Features Features of the watchdog timer are given below. • Incremented by internal clock source (φ/8192 or φw/32) on the H8/38024, H8/38024S, and H8/38024F-ZTAT Group. • On the H8/38124 Group, 10 internal clocks (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or watchdog on-chip oscillator) are available for selection for use by...
Page 321 Figures 9.17(1) and 9.17(2) show a block diagram of the watchdog timer. TCSRW φ φ/8192 φ [Legend] Reset TCSRW: Timer control/status register W signal TCW: Timer counter W PSS: Prescaler S Figure 9.17(1) Block Diagram of Watchdog Timer (H8/38024, H8/38024S, H8/38024F-ZTAT Group) Rev. 6.00, 08/04, page 291 of 628...
Page 322 Watchdog on-chip TCSRW oscillator φ φ Interrupt/reset Internal reset signal or controller interrupt request signal [Legend] TCSRW: Timer control/status register W TCW: Timer counter W TMW: Timer mode register W PSS: Prescaler S Figure 9.17(2) Block Diagram of Watchdog Timer (H8/38124 Group) Register Configuration Table 9.16 shows the register configuration of the watchdog timer.
Page 323: Register Descriptions
Notes: 1. Write is enabled only under certain conditions, which are given in the descriptions of the individual bits. 2. Initial value is 0 on H8/38024, H8/38024S, and H8/38024F-ZTAT Group; initial value is 1 on H8/38124 Group. TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself, controls watchdog timer operations, and indicates operating status.
Page 324 Bit 5—Bit 4 Write Disable (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI Description Bit 4 is write-enabled Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 4—Timer Control/Status Register W Write Enable (TCSRWE) Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Page 325 Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, but sets WDON to 1 on the H8/38124 Group.
Page 326 Initial value Read/Write For the H8/38024, H8/38024S, and H8/38024F-ZTAT groups, the clock source is φ/8,192 or φw/32. For the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS is 1.
Page 327 Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Description Internal clock: φ/64 count Internal clock: φ/128 count Internal clock: φ/256 count Internal clock: φ/512 count Internal clock: φ/1024 count Internal clock: φ/2048 count Internal clock: φ/4096 count Internal clock: φ/8192 count (initial value) Watchdog on-chip oscillator...
Page 328 8, I/O Ports. Bit 2—Watchdog Timer Source Clock Select (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different. • H8/38024, H8/38024S, H8/38024F-ZTAT Group...
Page 329: Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1.
Page 330: Watchdog Timer Operation States
9.6.4 Watchdog Timer Operation States Table 9.17(1) and table 9.17(2) summarize the watchdog timer operation states for the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, and for the H8/38124 Group, respectively. Table 9.17(1) Watchdog Timer Operation States (H8/38024, H8/38024S, H8/38024F-ZTAT Group) Operation...
Page 331: Asynchronous Event Counter (Aec)
Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock or internal clock input. Features Features of the asynchronous event counter are given below. • Can count asynchronous events Can count external events input asynchronously without regard to the operation of base clocks φ...
Page 332 Block Diagram Figure 9.19 shows a block diagram of the asynchronous event counter. IRREC ECCR φ ECCSR φ/2 φ/4, φ/8 (8 bits) Edge sensing AEVH circuit (8 bits) Edge sensing AEVL circuit Edge sensing IRQAEC To CPU interrupt circuit (IRREC2) ECPWCRL ECPWCRH PWM waveform generator...
Page 333 Pin Configuration Table 9.18 shows the asynchronous event counter pin configuration. Table 9.18 Pin Configuration Name Abbr. Function Asynchronous event input H AEVH Input Event input pin for input to event counter H Asynchronous event input L AEVL Input Event input pin for input to event counter L Event input enable interrupt input IRQAEC Input Input pin for interrupt enabling event input...
Page 334: Register Configurations
9.7.2 Register Configurations Event Counter PWM Compare Register H (ECPWCRH) ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value Read/Write Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH should not be modified. When changing the conversion period, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWCRH.
Page 335 Event Counter PWM Data Register H (ECPWDRH) ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Initial value Read/Write Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH.
Page 336 Bits 7 and 6—AEC Edge Select H Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin. Bit 7 Bit 6 AHEGS1 AHEGS0 Description Falling edge on AEVH pin is sensed (initial value) Rising edge on AEVH pin is sensed Both edges on AEVH pin are sensed Use prohibited Bits 5 and 4—AEC Edge Select L...
Page 337 Bit 1—Event Counter PWM Enable Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC. Bit 1 ECPWME Description AEC PWM halted, IRQAEC selected (initial value) AEC PWM operation enabled, IRQAEC deselected Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1.
Page 338 Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0) Bits 5 and 4 select the clock used by ECL. Bit 5 Bit 4 ACKL1 ACKL0 Description AEVL pin input (initial value) φ/2 φ/4 φ/8 Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0) Bits 3 to 1 select the event counter PWM clock.
Page 339 Event Counter Control/Status Register (ECCSR)  CUEH CUEL CRCH CRCL Initial Value R/W * R/W * Read/Write Note: Bits 7 and 6 can only be written with 0, for flag clearing. ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function.
Page 340 Bit 6 Description ECL has not overflowed (initial value) Clearing condition: After reading OVL = 1, cleared by writing 0 to OVL ECL has overflowed Setting condition: Set when ECL overflows from H'FF to H'00 Bit 5—Reserved Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4—Channel Select (CH2) Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels.
Page 341 Bit 2—Count-up Enable L (CUEL) Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held.
Page 342 counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software, and is also initialized to H'00 upon reset. Event Counter L (ECL) ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0 Initial Value Read/Write ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH.
Page 343: Operation
9.7.3 Operation 16-bit Event Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of bits ACKL1 and ACKL0 in ECCR.
Page 344 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Page 345 IRQAEC Operation When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC.
Page 346 Figure 9.22 and table 9.20 show examples of event counter PWM operation. = T × (N Clock input enabled time Clock input disabled time : One conversion period ECPWM input clock cycle Value of ECPWDRH and ECPWDRL Fixed low when Ndr = H'FFFF = T ×...
Page 347: Asynchronous Event Counter Operation Modes
Figure 9.23 shows an example of the operation of this function. Input event IRQAEC or IECPWM Edge generated by clock return Actually counted clock source Counter value Clock stopped Figure 9.23 Example of Clock Control Operation 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21.
Page 348: Application Notes
9.7.5 Application Notes 1. When reading the values in ECH and ECL, the correct value will not be returned if the event counter increments during the read operation. Therefore, if the counter is being used in the 8- bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
Page 349: Section 10 Serial Communication Interface
Section 10 Serial Communication Interface 10.1 Overview The H8/38024 Group is provided with one serial communication interface, SCI3. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. It is also provided with a multiprocessor communication function that enables serial data to be transferred among processors.
Page 350 • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception. • On-chip baud rate generator, allowing any desired bit rate to be selected •...
Page 351: Block Diagram
10.1.2 Block Diagram Figure 10.1 shows a block diagram of SCI3. Internal clock (φ/64, φ/16, φ /2, φ) External Baud rate generator clock Clock Transmit/receive SCR3 control circuit SPCR Interrupt request (TEI, TXI, RXI, ERI) [Legend] RSR: Receive shift register RDR: Receive data register TSR:...
Page 352: Pin Configuration
10.1.3 Pin Configuration Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration Name Abbr. Function SCI3 clock SCI3 clock input/output SCI3 receive data input Input SCI3 receive data input SCI3 transmit data output Output SCI3 transmit data output 10.1.4 Register Configuration Table 10.2 shows the SCI3 register configuration.
Page 353: Register Descriptions
10.2 Register Descriptions 10.2.1 Receive Shift Register (RSR)         Read/Write RSR is a register used to receive serial data. Serial data input to RSR from the RXD pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically.
Page 354: Transmit Shift Register (Tsr)
10.2.3 Transmit Shift Register (TSR)         Read/Write TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD pin in order, starting from the LSB (bit 0).
Page 355: Serial Mode Register (Smr)
10.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value Read/Write SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Page 356 Bit 5—Parity Enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 Description Parity bit addition and checking disabled *...
Page 357 Bit 3—Stop Bit Length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added.
Page 358: Serial Control Register 3 (Scr3)
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, Bit rate register (BRR).
Page 359 Bit 7—Transmit Interrupt Enable (TIE) Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when transmit data is transferred from the transmit data register (TDR) to the transmit shift register (TSR), and bit TDRE in the serial status register (SSR) is set to 1. TXI can be released by clearing bit TDRE or bit TIE to 0.
Page 360 Bit 4—Receive Enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 Description Receive operation disabled * (RXD32 pin is I/O port) (initial value) Receive operation enabled * (RXD32 pin is receive data pin) Notes: 1.
Page 361 Bit 2—Transmit End Interrupt Enable (TEIE) Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid transmit data in TDR when MSB data is to be sent. Bit 2 TEIE Description Transmit end interrupt request (TEI) disabled (initial value) Transmit end interrupt request (TEI) enabled * Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by...
Page 362: Serial Status Register (Ssr)
10.2.7 Serial Status Register (SSR) TDRE RDRF TEND MPBR MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and multiprocessor bits.
Page 363 Bit 6—Receive Data Register Full (RDRF) Bit 6 indicates that received data is stored in RDR. Bit 6 RDRF Description There is no receive data in RDR (initial value) Clearing conditions: After reading RDRF = 1, cleared by writing 0 to RDRF When RDR data is read by an instruction There is receive data in RDR Setting condition:...
Page 364 Bit 4—Framing Error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode. Bit 4 Description Reception in progress or completed * (initial value) Clearing condition: After reading FER = 1, cleared by writing 0 to FER A framing error has occurred during reception Setting condition: When the stop bit at the end of the receive data is checked for a value...
Page 365 Bit 2—Transmit End (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified. Bit 2 TEND Description Transmission in progress Clearing conditions: After reading TDRE = 1, cleared by writing 0 to TDRE When data is written to TDR by an instruction...
Page 366: Bit Rate Register (Brr)
10.2.8 Bit Rate Register (BRR) BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Page 367 Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) 10 MHz 16 MHz Bit Rate Error Error (bit/s) 0.88 –1.36 1.73 0.16 1.73 –2.34 –2.34 3 –2.34 1.73 0.16 1.73 0.16 1200 1.73 0.16 2400 1.73 103 0.16 4800 1.73...
Page 368 Table 10.4 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φw/2 * /φw * φ/16 φ/64 Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Page 369 Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) 38.4 kHz 2 MHz 4 MHz Bit Rate Error Error Error (bit/s)
Page 370 Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) 10 MHz 16 MHz Bit Rate Error Error (bit/s) — — — — — — — — — — — — — — — — — — —...
Page 371 Table 10.7 Relation between n and Clock SMR Setting Clock CKS1 CKS0 φ φ /2 * /φw * φ/16 φ/64 Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φw clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Page 372: Clock Stop Register 1 (Ckstpr1)
10.2.9 Clock stop register 1 (CKSTPR1)   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value   Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Page 373 Bit 5—P4 /TXD Pin Function Switch (SPC32) This bit selects whether pin P4 /TXD is used as P4 or as TXD Bit 5 SPC32 Description Functions as P4 I/O pin (initial value) output pin * Functions as TXD Note: * Set the TE bit in SCR3 after setting this bit to 1. Bit 4—Reserved Bit 4 is reserved;...
Page 374: Operation
10.3 Operation 10.3.1 Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
Page 375 Table 10.8 SMR Settings and Corresponding Data Transfer Formats Data Transfer Format bit 7 bit 6 bit 2 bit 5 bit 3 Data Multiprocessor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data No 1 bit mode 2 bits 1 bit 2 bits 7-bit data...
Page 376 Table 10.9 SMR and SCR3 Settings and Clock Source Selection SCR3 Bit 7 Bit 1 Bit 0 Transmit/Receive Clock COM CKE1 CKE0 Mode Clock Source SCK Pin Function Asynchronous Internal I/O port (SCK pin not used) mode Outputs clock with same frequency as bit rate External Inputs clock with frequency 16 times bit rate Synchronous...
Page 377 RSR (reception in progress) RSR↑ (reception completed, transfer) RDRF ← 1 RDRF = 0 (RXI request when RIE = 1) Figure 10.2(a) RDRF Setting and RXI Interrupt TDR (next transmit data) ↓ TSR (transmission in progress) TSR (transmission completed, transfer) TDRE ←...
Page 378: Operation In Asynchronous Mode
10.3.2 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Page 379 Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.11 Data Transfer Formats (Asynchronous Mode) Serial Data Transfer Format and Frame Length STOP 10 11 12 8-bit data...
Page 380 Clock Either an internal clock generated by the baud rate generator or an external clock input at the pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
Page 381 Figure 10.5 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set clock selection in SCR3. Be sure to Set bits CKE1 clear the other bits to 0. If clock output and CKE0 is selected in asynchronous mode, the clock is output immediately after setting...
Page 382 • Transmitting Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then write transmit data to the transmit...
Page 383 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 384 • Receiving Figure 10.8 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, Read bits OER, PER, and FER in the PER, FER in SSR serial status register (SSR) to determine if there is an error.
Page 385 If a receive error has Start receive occurred, read bits OER, error processing Overrun error PER, and FER in SSR to processing identify the error, and after carrying out the necessary error processing, ensure OER = 1? that bits OER, PER, and FER are all cleared to 0.
Page 386 SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received.
Page 387: Operation In Synchronous Mode
Figure 10.9 shows an example of the operation when receiving in asynchronous mode. Start Receive Parity Stop Start Receive Parity Stop Mark state data data (idle state) Serial data 1 frame 1 frame RDRF RXI request RDRF 0 start bit ERI request in operation cleared to 0...
Page 388 Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.10. Serial clock Serial Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 data Don't Don't 8 bits care care One transfer data unit (character or frame)
Page 389: Data Transfer Operations
Data Transfer Operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2, 3. SCI3 initialization, and shown in figure 10.5. • Transmitting Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Page 390 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 391 • Receiving Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER Read bit OER in the serial status register in SSR (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing.
Page 392 SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Page 393: Synchronous Mode
• Simultaneous transmit/receive Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read the serial status register (SSR) and Read bit TDRE check that bit TDRE is set to 1, then write in SSR...
Page 394: Multiprocessor Communication Function
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2.
Page 395 Sender Communication line Receiver A Receiver B Receiver C Receiver D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle Data transmission cycle (specifying the receiver) (sending data to the receiver specified by the ID) MPB: Multiprocessor bit...
Page 396 Start Sets bit SPC32 to 1 in SPCR Read bit TDRE Read the serial status register (SSR) in SSR and check that bit TDRE is set to 1, then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register (TDR).
Page 397 SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Page 398 Start Set bit MPIE to 1 in SCR3. Set bit MPIE to 1 in SCR3 Read bits OER and FER in the serial status register (SSR) to determine if there is an error. If a receive error has Read bits OER occurred, execute receive error processing.
Page 399 Start receive error processing Overrun error processing OER = 1? Break? FER = 1? Framing error processing Clear bits OER and FER to 0 in SSR End of receive error processing Figure 10.19 Example of Multiprocessor Data Reception Flowchart (cont) Figure 10.20 shows an example of the operation when receiving using the multiprocessor format.
Page 400 Start Receive Stop Start Receive data Stop Mark state data (ID1) (Data1) (idle state) Serial data 1 frame 1 frame MPIE RDRF value RXI request RDRF cleared No RXI request operation MPIE cleared to 0 RDR retains to 0 previous state User RDR data read When data is not...
Page 401: Interrupts
10.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.13. Table 10.13 SCI3 Interrupt Requests Vector Interrupt Abbr.
Page 402: Application Notes
10.5 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically.
Page 403 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD directly. In a break, the input from the RXD pin becomes all 0s, with the result that bit FER is set and bit PER may also be set.
Page 404 16 clock pulses 8 clock pulses 15 0 15 0 Internal basic clock Receive data Start bit (RXD32) Synchronization sampling timing Data sampling timing Figure 10.21 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1).
Page 405 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred.
Page 406 9. Switching SCK function If pin SCK is used as a clock output pin by SCI3 in synchronous mode and is then switched to a general input/output pin (a pin with a different function), the pin outputs a low level signal for half a system clock (φ) cycle immediately after it is switched.
Page 407: Section 11 10-Bit Pwm
11.1 Overview The H8/38024 Group is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM.
Page 408: Block Diagram
11.1.2 Block Diagram Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/38024 Group, H8/38024F- ZTAT Group, and H8/38024S Group. Figure 11.1(2) shows a block diagram of the 10-bit PWM of the H8/38124 Group. PWDRLm PWDRUm φ/2 φ/4...
Page 409: Pin Configuration
PWDRLm PWDRUm φ/2 φ/4 PWM waveform φ/8 generator φ PWCRm IECPWM PWMm (IECPWM) [Legend] m = 1 or 2 PWCRm: PWM control register PWDRLm: PWM data register L PWDRUm: PWM data register U PWMm: PWM output pin IECPWM: Event counter PWM (PWM incorporating AEC) Figure 11.1(2) Figure 11.1(1) Block Diagram of the 10-bit PWM (H8/38124 Group: 1-Channel Configuration) 11.1.3...
Page 410: Register Configuration
Read/Write Note: * Implemented on H8/38124 Group only. On the H8/38024 Group, H8/38024F-ZTAT Group, and H8/38024S Group, PWCRm is an 8-bit write-only register for input clock selection. Upon reset, PWCRm is initialized to H'FC. On the H8/38124 Group, PWCRm is an 8-bit write- only register used to select the input clock and PWM output type.
Page 411 Bit 2—Output Format Select (PWCRm2)* This bit selects the format of the output from the PWMm output pin. This bit is write-only. Reading it always returns 1. Bit 2 PWCRm2 Description Pulse-division PWM (initial value) Event counter PWM Note: * Implemented on H8/38124 Group only. Bits 1 and 0—Clock Select 1 and 0 (PWCRm1, PWCRm0) Bits 1 and 0 select the clock supplied to the 10-bit PWM.
Page 412: Pwm Data Registers U And L (Pwdrum, Pwdrlm)
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm) PWDRUm       PWDRUm1 PWDRUm0 Initial value       Read/Write PWDRLm PWDRLm7 PWDRLm6 PWDRLm5 PWDRLm4 PWDRLm3 PWDRLm2 PWDRLm1 PWDRLm0 Initial value Read/Write PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to PWDRUm and the lower 8 bits to PWDRLm.
Page 413: Clock Stop Register 2 (Ckstpr2)
11.2.3 Clock Stop Register 2 (CKSTPR2) LVDCKSTP * — — PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value Read/Write — — Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules.
Page 414: Operation
11.3 Operation 11.3.1 Operation When using the 10-bit PWM, set the registers in the following sequence. 1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P9 /PWM1 or /PWM2 is designated as the PWM output pin. 2.
Page 415: Pwm Operation Modes
1 conversion period Figure 11.2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11.3. Table 11.3 PWM Operation Modes Operation Sub- Sub- Module Mode Reset Active Sleep Watch active sleep Standby Standby PWCRm Reset Functions Functions Retained Retained Retained Retained Retained PWDRUm Reset Functions Functions Retained Retained Retained Retained Retained...
Page 416 Rev. 6.00, 08/04, page 386 of 628...
Page 417: Section 12 A/D Converter
Section 12 A/D Converter 12.1 Overview This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution • Eight input channels •...
Page 418: Block Diagram
12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ),64/ ADSR Multiplexer Com- Control logic parator Reference voltage ADRRH ADRRL IRRAD [Legend] AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag Figure 12.1 Block Diagram of the A/D Converter Rev.
Page 419: Pin Configuration
12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr. Function Analog power supply Input Power supply and reference voltage of analog part Analog ground Input Ground and reference voltage of analog part Analog input 0 Input Analog input channel 0...
Page 420: Register Descriptions
12.2 Register Descriptions 12.2.1 A/D Result Registers (ADRRH, ADRRL)       ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0       Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde-...
Page 421 31 µs —* —* Note: * For the H8/38024, H8/38024S, H8/38024F-ZTAT, and H8/38124 groups, operation is not guaranteed if the conversion time is less than 7.8 µs. A conversion time of 7.8 µs or greater should be selected. Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a value of at least 12.4 µs.
Page 422: A/D Start Register (Adsr)
Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected (initial value) Setting prohibited *: Don’t care 12.2.3 A/D Start Register (ADSR) ADSF — — — — — — — Initial value Read/Write — — — —...
Page 423: Clock Stop Register 1 (Ckstpr1)
Bits 6 to 0—Reserved Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.4 Clock Stop Register 1 (CKSTPR1)   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value   Read/Write CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules.
Page 424: Operation
12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10- bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
Page 425: A/D Converter Operation Modes
12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12.3. Table 12.3 A/D Converter Operation Modes Operation Sub- Sub- Module Mode Reset Active Sleep Watch active sleep Standby Standby Reset Functions Functions Retained Retained Retained Retained Retained ADSR Reset Functions Functions Retained Retained Retained Retained Retained...
Page 426 Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. Figure 12.3 Typical A/D Converter Operation Timing Rev. 6.00, 08/04, page 396 of 628...
Page 427 Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR ADSF = 0? Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) Rev.
Page 428: A/D Conversion Accuracy Definitions
Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Perform A/D conversion? Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) 12.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below.
Page 429 • Nonlinearity error The error with respect to the ideal A/D conversion characteristics between zero voltage and full-scale voltage. Does not include offset error, full-scale error, or quantization error. • Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, full- scale error, quantization error, and nonlinearity error.
Page 430: Application Notes
12.7 Application Notes 12.7.1 Application Notes • Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. • Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy.
Page 431 This LSI A/D converter equivalent circuit Sensor output impedance 10 kΩ Up to 10 kΩ Sensor input Low-pass 20 pF 15 pF filter C to 0.1 µF Figure 12.8 Analog Input Circuit Example Rev. 6.00, 08/04, page 401 of 628...
Page 432 Rev. 6.00, 08/04, page 402 of 628...
Page 433: Section 13 Lcd Controller/Driver
Section 13 LCD Controller/Driver 13.1 Overview This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features Features of the LCD controller/driver are given below. •...
Page 434: Block Diagram
LCD RAM (16 bytes) [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 13.1(1) Block Diagram of H8/38024, H8/38024S, and H8/38024F-ZTAT Group LCD Controller/Driver Rev. 6.00, 08/04, page 404 of 628...
Page 435 LCD drive power supply φ/256 to φ/2 Common Common φ w data latch driver LPCR LCR2 32-bit Segment shift Display timing generator driver register LCD RAM (16 bytes) SEGn [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 13.1(2) Block Diagram of H8/38124 Group LCD Controller/Driver Rev.
Page 436: Pin Configuration
13.1.3 Pin Configuration Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr. Function Segment output pins to SEG Output LCD segment drive pins All pins are multiplexed as port pins (setting programmable) Common output pins to COM Output LCD common drive pins...
Page 437: Register Descriptions
13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR)  DTS1 DTS0 SGS3 SGS2 SGS1 SGS0  Initial value Read/Write LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions. Bits 7 to 5—Duty Cycle Select 1 and 0 (DTS1, DTS0), Common Function Select (CMX) The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty.
Page 438 Function of Pins SEG to SEG Bit 3 Bit 2 Bit 1 Bit 0 SGS3 SGS2 SGS1 SGS0 Notes Port Port Port Port Port Port Port Port (Initial value) Port Port Port Port Port Port Port Port Port Port Port Port Port Port...
Page 439: Lcd Control Register (Lcr)
13.2.2 LCD Control Register (LCR)  DISP CKS3 CKS2 CKS1 CKS0 Initial value  Read/Write LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset. Bit 7—Reserved Bit 7 is reserved;...
Page 440 Bit 4—Display Data Control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description Blank data is displayed (initial value) LCD RAM data is display Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Page 441: Lcd Control Register 2 (Lcr2)
Read/Write — — Note: * Applies to the H8/38124 Group only. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, these bits are reserved like bit 4. LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform and removal of split-resistance.
Page 442 Bits 3 to 0—Removal of Split-Resistance Control These bits control whether the split-resistance is removed or connected. Note that on products other than the H8/38124 Group, these bits are reserved like bit 4. Bit 3 Bit 2 Bit 1 Bit 0 CDS3 CDS2 CDS1...
Page 443: Clock Stop Register 2 (Ckstpr2)
13.2.4 Clock Stop Register 2 (CKSTPR2)   LVDCKSTP * PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value   Read/Write Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules.
Page 444: Operation
13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V and V as shown in figure 13.2.
Page 445 Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS to SGS c.
Page 446: Relationship Between Lcd Ram And Display
13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on.
Page 447 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H'F74F SEG32 SEG32 SEG32 SEG31 SEG31 SEG31 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.4 LCD RAM Map (1/3 Duty) Rev.
Page 448 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'F740 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Display space SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 H'F747 Space not used for display H'F74F COM2 COM1...
Page 449 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame Data Data COM1 COM1 COM2 SEGn SEGn (d) Waveform with static output (c) Waveform with 1/2 duty M: LCD alternation signal Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
Page 450 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Data Data COM1 COM1 COM2 COM2 COM3 COM3 COM4 SEGn SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame...
Page 451: Operation In Power-Down Modes
Table 13.3 Output Levels Data Static Common output Segment output 1/2 duty Common output Segment output 1/3 duty Common output Segment output 1/4 duty Common output Segment output M: LCD alternation signal 13.3.3 Operation in Power-Down Modes This LSI the LCD controller/driver can be operated even in the power-down modes. The operating state of the LCD controller/driver in the power-down modes is summarized in table 13.4.
Page 452: Boosting The Lcd Drive Power Supply
13.3.4 Boosting the LCD Drive Power Supply When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power supply capacity is insufficient when V is used as the power supply, the power supply impedance must be reduced.
Page 453: Section 14 Power-On Reset And Low-Voltage Detection Circuits (H8/38124 Group Only)
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.1 Overview This LSI can include a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits. This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the power supply voltage fall and to recreate the state before the power supply voltage fall when the power supply voltage rises again.
Page 454: Block Diagram
14.1.2 Block Diagram A block diagram of the power-on reset circuit and low-voltage detection circuit are shown in figure 14.1. φ Internal reset Noise signal canceler Power-on reset circuit Noise canceler LVDCR Vreset Ladder − External resistor LVDRES power Vint supply Interrupt LVDSR...
Page 455: Pin Description
14.1.3 Pin Description The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1. Table 14.1 Pin Description Symbol Function Low-voltage detection circuit Vref Input Reference voltage input for low- reference voltage input pin voltage detection circuit Low-voltage detection circuit power extD Input...
Page 456 voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the low- voltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power supply voltage drops or rises. Bit 7—LVD Enable (LVDE) This bit is used to control whether or not the low-voltage detection circuit is used. Bit 7 LVDE Description...
Page 457 Bit 3—LVDR Detection Level Select (LVDSEL) This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset. Bit 3 LVDSEL Description...
Page 458: Low-Voltage Detection Status Register (Lvdsr)
Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table 14.3 when making settings to LVDCR. Table 14.3 LVDCR Settings and Function Selections Low-Voltage Low-Voltage LVDCR Setting Value Low-Voltage Detection Detection Power-on Voltage Drop Voltage Rise Detection LVDE LVDSEL LVDRE LVDDE LVDUE...
Page 459 Bits 6 to 4—Reserved These bits are read/write enabled reserved bits. Bit 3—Reference Voltage External Input Select (VREFSEL) This bit is used to select the reference voltage. Bit 3 VREFSEL Description The on-chip circuit is used to generate the reference voltage (initial value) The reference voltage is input to the Vref pin from an external source Bit 2—Reserved...
Page 460: Low-Voltage Detection Counter (Lvdcnt)
14.2.3 Low-Voltage Detection Counter (LVDCNT) CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Initial value Read/Write LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The counter increments using φ/4 as the clock source until it overflows by switching from H'FF to H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip reference voltage generator has stabilized.
Page 461: Operation
14.3 Operation 14.3.1 Power-On Reset Circuit Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Page 462: Low-Voltage Detection Circuit
14.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for 150 µs (t ) until the reference voltage and the low-voltage-detection power supply have LVDON...
Page 463 LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150 µs (t ) until the reference voltage and the low-voltage-detection power supply have stabilized, LVDON...
Page 464 The reference voltage, power supply voltage drop detection level, and power supply voltage rise detection level can be input to the LSI from external sources via the Vref, extD, and extU pins. Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins. First, make sure that the voltages input to pins extD and extU are set to higher levels than the interrupt detection voltage Vexd.
Page 465 Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU. LVDCR LVDRES − On-chip ladder resistor LVDINT External power − supply voltage R1 = Interrupt 517 kΩ LVDSR extD controller R2 = 33 kΩ Interrupt extU request...
Page 466 Resistance Value Calculation Table R (kΩ Ω Ω Ω ) R1 (kΩ Ω Ω Ω ) R2 (kΩ Ω Ω Ω ) R3 (kΩ Ω Ω Ω ) Ex. No Vref (V) Vreset1 Vint(D) Vint(U) 1.30 1000 1.41 1000 1.57 1000 2.09 1000...
Page 467 Operation and Cancellation Setting Procedure Using LVDR and LVDI: Settings should be made as indicated below in order to ensure proper operation of the low voltage detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage detection circuit operation and cancellation.
Page 468 Rev. 6.00, 08/04, page 438 of 628...
Page 469: Section 15 Power Supply Circuit (H8/38124 Group Only)
Section 15 Power Supply Circuit (H8/38124 Group Only) This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external V pin.
Page 470: When Not Using Internal Power Supply Step-Down Circuit
15.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the CV pin and V pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply.
Page 471: Section 16 Electrical Characteristics
Section 16 Electrical Characteristics 16.1 H8/38024 ZTAT Version and Mask ROM Version Absolute Maximum Ratings Table 16.1 lists the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 Analog power supply voltage –0.3 to +7.0...
Page 472: H8/38024 Ztat Version And Mask Rom Version Electrical Characteristics
16.2 H8/38024 ZTAT Version and Mask ROM Version Electrical Characteristics 16.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 16.0...
Page 473 Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 474: Dc Characteristics
16.2.2 DC Characteristics Table 16.2 lists the DC characteristics of the H8/38024. Table 16.2 DC Characteristics = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications), T...
Page 475 Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES, Input low –0.3 — 0.2 V = 4.0 V to 5.5 V to WKP voltage –0.3 — 0.1 V Except the above , IRQ , IRQ IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK , UD...
Page 476 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Output low , P1 — — = 4.0 V to 5.5 V voltage , P1 = 1.6 mA to P4 — — = 0.4 mA to P5 — — = 0.4 mA to P6 to P7 to P8...
Page 477 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Pull-up –I , P1 50.0 — 300.0 µA = 5 V, , P1 = 0 V current to P3 to P5 — 35.0 — = 2.7 V, Reference to P6 = 0 V value Input...
Page 478 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Watch — µA = 2.7 V, WATCH mode 32 kHz crystal current oscillator dissipation LCD not used Standby — µA 32 kHz crystal STBY mode oscillator not used current dissipation RAM data —...
Page 479 Notes: Connect the TEST pin to V 1. Applies to the Mask ROM products. 2. Applies to the HD64738024. 3. Pin states during current measurement. Other LCD Power Mode Internal State Pins Supply Oscillator Pins Active (high-speed) Operates Halted System clock oscillator: mode (I crystal OPE1...
Page 480: Ac Characteristics
16.2.3 AC Characteristics Table 16.3 lists the control signal timing, and tables 16.4 lists the serial interface timing of the H8/38024. Table 16.3 Control Signal Timing = 1.8 V to 5.5 V, AV = 1.8 V to 5.5 V, V = AV = 0.0 V, T...
Page 481 Values Applicable Reference Item Symbol Pins Unit Test Condition Figure External clock high — — = 4.5 V to 5.5 V Figure 16.1 width — — = 2.7 V to 5.5 V — — Except the above — 15.26 — µs 13.02 External clock low...
Page 482 Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2). 2. The figure in parentheses applies when an external clock is used. 3. After powering on, hold V at 2.2 V to 5.5 V until the chip's oscillation settling time has elapsed.
Page 483: A/D Converter Characteristics
16.2.4 A/D Converter Characteristics Table 16.5 shows the A/D converter characteristics of the H8/38024. Table 16.5 A/D Converter Characteristics = 1.8 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications), T = +75°C (Die) unless otherwise indicated.
Page 484: Lcd Characteristics
Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Absolute — — ±3.0 = 2.7 V to 5.5 V accuracy = 2.7 V to 5.5 V — — ±6.0 = 2.0 V to 5.5 V = 2.0 V to 5.5 V —...
Page 485: H8/38024 F-Ztat Version And H8/38024R F-Ztat Version Absolute Maximum Ratings
16.3 H8/38024 F-ZTAT Version and H8/38024R F-ZTAT Version Absolute Maximum Ratings Table 16.7 lists the absolute maximum ratings. Table 16.7 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +4.3 Analog power supply voltage –0.3 to +4.3...
Page 486: H8/38024 F-Ztat Version And H8/38024R F-Ztat Version Electrical Characteristics
16.4 H8/38024 F-ZTAT Version and H8/38024R F-ZTAT Version Electrical Characteristics 16.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4...
Page 487 Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 488: Dc Characteristics
16.4.2 DC Characteristics Table 16.8 lists the DC characteristics of the HD64F38024 and HD64F38024R. Table 16.8 DC Characteristics = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES,...
Page 489 Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES, Input low –0.3 — 0.1 V to WKP voltage , IRQ , IRQ IRQAEC, P9 AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, , UD –0.3 — 0.2 V –0.3 — 0.1 V –0.3 —...
Page 490 Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES, P4 Input/output — — µA = 0.5 V to leakage – 0.5 V current , P1 , P1 to P3 to P4 to P5 to P6 to P7 to P8 IRQAEC, to P9 to PA...
Page 491 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Active — — Active (medium- OPE2 mode speed) mode current = 3 V, Max. dissipation = 2 MHz guideline φ /128 = 1.1 × typ. — — Active (medium- speed) mode = 3 V, Max.
Page 492 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Subsleep — 16.0 µA = 2.7 V, SUBSP mode LCD on 32 kHz current crystal oscillator dissipation (φ =φ Watch — — µA = 2.7 V, WATCH mode = 25°C current 32 kHz crystal Reference...
Page 493 2. Applied when the PIOFF bit in the port mode register 9 is 1. 3. Pin states during current measurement. Other LCD Power Mode Internal State Pins Supply Oscillator Pins Active (high-speed) Operates Halted System clock oscillator: mode (I crystal OPE1 Subclock oscillator: Active (medium-...
Page 494: Ac Characteristics
16.4.3 AC Characteristics Table 16.9 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024F. Table 16.9 Control Signal Timing = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values...
Page 495 Values Applicable Reference Pins Figure Item Symbol Unit Test Condition External clock low — — Figure 16.1 width — 15.26 — µs 13.02 External clock rise — — Figure 16.1 time — — 55.0 External clock fall — — Figure 16.1 time —...
Page 496 Table 16.10 Serial Interface (SCI3) Timing = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Reference Item Symbol Unit Test Conditions Figure Input clock Asynchronous — — Figure 16.4 scyc cycle Synchronous...
Page 497: A/D Converter Characteristics
16.4.4 A/D Converter Characteristics Table 16.11 shows the A/D converter characteristics of the H8/38024F. Table 16.11 A/D Converter Characteristics = 2.7 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Item Symbol Pins Unit Test Condition Figure Analog power —...
Page 498: Lcd Characteristics
16.4.5 LCD Characteristics Table 16.12 shows the LCD characteristics. Table 16.12 LCD Characteristics = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Test Item Symbol Pins Min Typ Max Unit Conditions Figure Segment driver...
Page 499: Flash Memory Characteristics
16.4.6 Flash Memory Characteristics Table 16.13 lists the flash memory characteristics. Table 16.13 Flash Memory Characteristics = 2.7 V to 3.6 V, V = AV = 0.0 V, V = 2.7 V to 3.6 V (operating voltage range in reading), V = 3.0 V to 3.6 V (operating voltage range in programming/erasing), T = –20 to +75°C (operating temperature range in programming/erasing)
Page 500 Notes: 1. Make the time settings in accordance with the program/erase algorithms. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) The time required to erase one block.
Page 501: H8/38024S Group Mask Rom Version Absolute Maximum Ratings
16.5 H8/38024S Group Mask ROM Version Absolute Maximum Ratings Table 16.14 lists the absolute maximum ratings. Table 16.14 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +4.3 Analog power supply voltage –0.3 to +4.3 Input voltage Ports other than Port B –0.3 to V +0.3...
Page 502: H8/38024S Group Mask Rom Version Electrical Characteristics
16.6 H8/38024S Group Mask ROM Version Electrical Characteristics 16.6.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 32.768 10.0 •...
Page 503 Power Supply Voltage and Operating Frequency Range 19.2 16.384 (0.5) 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz.
Page 504: Dc Characteristics
16.6.2 DC Characteristics Table 16.15 lists the DC characteristics of the H8/38024S. Table 16.15 DC Characteristics = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES,...
Page 505 Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES, Input low –0.3 — 0.1 V to WKP voltage , IRQ , IRQ IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK , UD –0.3 — 0.2 V –0.3 — 0.1 V –0.3 —...
Page 506 Values Item Symbol Applicable Pins Min Unit Test Condition Notes RES, P4 Input/output — — µA = 0.5 V to leakage – 0.5 V current , P1 , P1 to P3 to P4 to P5 to P6 to P7 to P8 IRQAEC, to P9 to PA...
Page 507 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Active — Active (high-speed) OPE1 mode mode current = 3 V, dissipation = 10 MHz — 0.03 — Active (medium- OPE2 speed) mode = 1.8 V, Max. = 1 MHz guideline φ...
Page 508 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Sleep mode — — = 3 V, SLEEP current = 4 MHz dissipation Max. guideline = 1.1 × typ. — = 3 V, = 10 MHz Subactive — — µA = 1.8 V, mode LCD on 32 kHz...
Page 509 Values Item Symbol Applicable Pins Min Unit Test Condition Notes Standby — — µA = 1.8 V, STBY mode = 25°C current 32 kHz crystal Reference dissipation oscillator not used value — — µA = 3.0 V, = 25°C 32 kHz crystal Reference oscillator not used value...
Page 510 Notes: Connect the TEST pin to V 1. Pin states during current measurement. Other LCD Power Mode Internal State Pins Supply Oscillator Pins Active (high-speed) Operates Halted System clock oscillator: mode (I crystal OPE1 Active (medium- Subclock oscillator: speed) mode (I Pin X = GND OPE2...
Page 511: Ac Characteristics
16.6.3 AC Characteristics Table 16.16 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024S. Table 16.16 Control Signal Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values...
Page 512 Values Reference Applicable Figure Item Symbol Pins Unit Test Condition External clock high — — = 2.7 V to 3.6 V Figure 16.1 width — — = 1.8 V to 3.6 V — 15.26 — µs 13.02 External clock low —...
Page 513 Table 16.17 Serial Interface (SCI3) Timing = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values Reference Item Symbol Unit Test Conditions Figure Input clock Asynchronous — — Figure 16.4 scyc cycle Synchronous...
Page 514: A/D Converter Characteristics
16.6.4 A/D Converter Characteristics Table 16.18 shows the A/D converter characteristics of the H8/38024S. Table 16.18 A/D Converter Characteristics = 1.8 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Pins Figure Item Symbol Unit Test Condition Analog power —...
Page 515: Lcd Characteristics
16.6.5 LCD Characteristics Table 16.19 shows the LCD characteristics. Table 16.19 LCD Characteristics = 1.8 V to 3.6 V, AV = 1.8 V to 3.6 V, V = AV = 0.0 V Values Applicable Reference Test Item Symbol Pins Min Typ Max Unit Conditions Figure Segment driver...
Page 516: Absolute Maximum Ratings Of H8/38124 Group
16.7 Absolute Maximum Ratings of H8/38124 Group Table 16.20 lists the absolute maximum ratings. Table 16.20 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage –0.3 to +7.0 –0.3 to +4.3 Analog power supply voltage –0.3 to +7.0 Input voltage Other than port B –0.3 to V...
Page 517: Electrical Characteristics Of H8/38124 Group
16.8 Electrical Characteristics of H8/38124 Group 16.8.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) 16.0 32.768 • Active (high-speed) mode • All operating modes • Sleep (high-speed) mode Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected) 32.768 •...
Page 518 Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected) 16.384 8.192 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 4.096 • Subactive mode 1000 • Subsleep mode (except CPU) • Watch mode (except CPU) 15.625 • Active (medium-speed) mode •...
Page 519 Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected) 16.384 8.192 4.096 0.35 • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 6.25 • Active (medium-speed) mode •...
Page 520 Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) 1000 • Active (medium-speed) mode • Active (high-speed) mode • Sleep (medium-speed) mode • Sleep (high-speed) mode Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected) 6.25 0.35...
Page 521: Dc Characteristics
16.8.2 DC Characteristics Table 16.21 lists the DC characteristics. Table 16.21 DC Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Item Symbol Applicable Pins Unit Test Condition Notes...
Page 522 Values Item Symbol Applicable Pins Unit Test Condition Notes RES, × 0.2 Input low – 0.3 — = 4.0 V to 5.5 V to WKP voltage , IRQ , IRQ IRQAEC, P9 × 0.1 – 0.3 — Other than above AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG,...
Page 523 Values Item Symbol Applicable Pins Unit Test Condition Notes Output low , P1 , P1 — — = 4.0 V to 5.5 V voltage to P4 = 1.6 mA to P5 to P6 — — = 0.4 mA to P7 to PA to P3 —...
Page 524 Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (high-speed) OPE1 mode mode Approx. current = 2.7 V, max. value = 1.1 × consump- = 2 MHz tion Typ. — — Approx. max. value = 1.1 × Typ.
Page 525 Values Item Symbol Applicable Pins Unit Test Condition Notes Active — — Active (medium- OPE2 mode speed) mode Approx. current = 2.7 V, max. value = 1.1 × consump- = 2 MHz, φ tion /128 Typ. — — Approx. max. value = 1.1 ×...
Page 526 Values Item Symbol Applicable Pins Unit Test Condition Notes Sleep — — = 2.7 V, SLEEP mode = 2 MHz Approx. current max. value = 1.1 × consump- tion Typ. — — Approx. max. value = 1.1 × Typ. — —...
Page 527 Values Item Symbol Applicable Pins Unit Test Condition Notes Watch — — µA = 2.7 V, WATCH mode = 25°C, Reference current 32-kHz crystal value consump- resonator used, — — tion LCD not used Reference value — = 2.7 V, 32-kHz crystal resonator used, LCD not used...
Page 528 Values Applicable Test Item Symbol Pins Unit Condition Notes Allowable output low Output pins — — = 4.0 V to current (per pin) except ports 3 5.5 V and 9 Port 3 — — 10.0 = 4.0 V to 5.5 V Output pins —...
Page 529 3. Pin states when current consumption is measured LCD Power RES Pin Mode Internal State Other Pins Supply Oscillator Pins Active (high-speed) Only CPU operates Stops System clock: mode (I crystal resonator OPE1 Active (medium- Subclock: speed) mode (I Pin X = GND OPE2 Sleep mode...
Page 530: Ac Characteristics
16.8.3 AC Characteristics Table 16.22 lists the control signal timing and table 16.23 lists the serial interface timing. Table 16.22 Control Signal Timing = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Reference...
Page 531 Values Applicable Reference Item Symbol Pins Unit Test Condition Figure IRQ0, IRQ1, Input pin high — — Figure 16.3 width IRQAEC, subcyc WKP0 to WKP7, AEVL, AEVH 0.5 — — IRQ0, IRQ1, Input pin low — — Figure 16.3 width IRQAEC, subcyc WKP0 to...
Page 532: A/D Converter Characteristics
16.8.4 A/D Converter Characteristics Table 16.24 shows the A/D converter characteristics. Table 16.24 A/D Converter Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Test Reference Item...
Page 533: Lcd Characteristics
16.8.5 LCD Characteristics Table 16.25 shows the LCD characteristics. Table 16.25 LCD Characteristics = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Values Applicable Reference Pins Figure Item Symbol Unit...
Page 534: Flash Memory Characteristics
16.8.6 Flash Memory Characteristics Table 16.26 Flash Memory Characteristics Condition: = 2.7 V to 5.5 V, V = AV = 0.0 V, V = 2.7 V to 5.5 V (range of operating voltage when reading), V = 3.0 V to 5.5 V (range of operating voltage when programming/erasing), T = –20°C to +75°C (range of operating temperature when programming/erasing: product with regular specifications, product with wide-...
Page 535 Values Test Item Symbol Unit Conditions Erase Wait time after — — µs SWE-bit setting * Wait time after — — µs ESU-bit setting * Wait time after — E-bit setting * α Wait time after — — µs E-bit clear * β...
Page 536: Power Supply Voltage Detection Circuit Characteristics
16.8.7 Power Supply Voltage Detection Circuit Characteristics Table 16.27 Power Supply Voltage Detection Circuit Characteristics (1) = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Rated Values Item Symbol Unit...
Page 537 Table 16.29 Power Supply Voltage Detection Circuit Characteristics (3) Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL and VINTUSEL = 1) Rated Values Item Symbol Unit Test Condition extD/extU interrupt Vexd 0.80 1.20 1.60 detection level VextD * extD/extU pin input –0.3...
Page 538 Table 16.30 Power Supply Voltage Detection Circuit Characteristics (4) Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL = Rated Values Test Item Symbol Unit Condition Vint(D) * – Power supply drop 3.08 * (Vref1 0.1) 3.08 * Vref1 3.08 * (Vref1 + 0.1) LVDSEL = 0...
Page 539: Power-On Reset Circuit Characteristics
Table 16. 31 Power Supply Voltage Detection Circuit Characteristics (5) Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL = VINTUSEL = 1) Rated Values Item Symbol Unit Test Condition Comparator detection Vcdl — — | VextU – Vref | accuracy | VextD –...
Page 540: Watchdog Timer Characteristics
16.8.9 Watchdog Timer Characteristics Table 16.33 Watchdog Timer Characteristics = 2.7 V to 5.5 V, V = AV = 0.0 V, unless otherwise specified Rated Values Applicable Test Item Symbol Pins Unit Note Condition On-chip oscillator — overflow time Note: * When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time remaining until an internal reset is generated.
Page 541 , IRQ , IRQ , IRQ TMIC, TMIF, TMIG, ADTRG, WKP to WKP IRQAEC, AEVL, AEVH Figure 16.3 Input Timing SCKW scyc Figure 16.4 SCK3 Input Clock Timing Rev. 6.00, 08/04, page 511 of 628...
Page 542 scyc or V or V (transmit data) (receive data) Note: * Output timing reference levels Output high = 1/2Vcc + 0.2 V Output low = 0.8 V Load conditions are shown in figure 16.7. Figure 16.5 SCI3 Synchronous Mode Input/Output Timing Figure 16.6 UD Pin Minimum Transition Width Timing Rev.
Page 543: Output Load Circuit
16.10 Output Load Circuit 2.4 kΩ Output pin 30 pF 12 kΩ Figure 16.7 Output Load Condition 16.11 Resonator Equivalent Circuit Crystal Resonator Parameters Ceramic Resonator Parameters Frequency Frequency 4.193 (MHz) (MHz) 100 Ω 100 Ω 30 Ω 18.3 Ω 6.8 Ω...
Page 544: Usage Note
Crystal Resonator Parameters Ceramic Resonator Parameters (1) (Manufacturer's Publicly Released Values) (Manufacturer's Publicly Released Values) Frequency Frequency Manufacturer Manufacturer (MHz) (MHz) 100 Ω 18.3 Ω Murata Manufacturing Co., Ltd. (max) Nihon Dempa Kogyo Co., Ltd. (max) (max) 16 pF (max) 36.94 pF Ceramic Resonator Parameters (2) (Manufacturer's Publicly Released Values)
Page 545: Appendix A Cpu Instruction Set
Appendix A CPU Instruction Set Instructions Operation Notation Rd8/16 General register (destination) (8 or 16 bits) Rs8/16 General register (source) (8 or 16 bits) Rn8/16 General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter...
Page 546 Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B #xx:8 → Rd8   0  2 MOV.B #xx:8, Rd B Rs8 → Rd8 ...
Page 547 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8+#xx:8 → Rd8  ADD.B #xx:8, Rd B Rd8+Rs8 → Rd8  ADD.B Rs, Rd W Rd16+Rs16 → Rd16  (1) ADD.W Rs, Rd B Rd8+#xx:8 +C →...
Page 548 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B Rd8 × Rs8 → Rd16       14 MULXU.B Rs, Rd B Rd16÷Rs8 → Rd16   (5) (6)   14 DIVXU.B Rs, Rd (RdH: remainder, RdL: quotient)
Page 549 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C   ROTL.B Rd   ROTR.B Rd B (#xx:3 of Rd8) ← 1       2 BSET #xx:3, Rd B (#xx:3 of @Rd16) ← 1 ...
Page 550 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C B (#xx:3 of Rd8) → Z      2 BTST #xx:3, Rd B (#xx:3 of @Rd16) → Z      6 BTST #xx:3, @Rd B (#xx:3 of @aa:8) →...
Page 551 Addressing Mode/ Instruction Length (bytes) Condition Code Branching Mnemonic Operation Condition I H N Z V C B C∨(#xx:3 of @aa:8) → C      BIOR #xx:3, @aa:8 B C⊕(#xx:3 of Rd8) → C      BXOR #xx:3, Rd ...
Page 552 Addressing Mode/ Instruction Length (bytes) Condition Code Mnemonic Operation I H N Z V C  SP−2 → SP       6 JSR @Rn PC → @SP PC ← Rn16  SP−2 → SP       8 JSR @aa:16 PC →...
Page 553: Operation Code Map
Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Page 554 Table A.2 Operation Code Map Rev. 6.00, 08/04, page 524 of 628...
Page 555: Number Of Execution States
Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The total number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I •...
Page 556 Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation N Instruction Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd...
Page 557 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR...
Page 558 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic BTST BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 CMP. B #xx:8, Rd CMP. B Rs, Rd CMP.W Rs, Rd DAA.B Rd DAS.B Rd DEC.B Rd...
Page 559 Instruction Branch Stack Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) MOV.W Rs, @–Rd MOV.W Rs, @aa:16 MULXU MULXU.B Rs, Rd NEG.B Rd NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC #xx:8, CCR ROTL...
Page 560: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Upper Address: H'F0 Bit Names Lower Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'20 FLMCR1 — H'21 FLMCR2 FLER — —...
Page 561 Upper Address: H'FF Bit Names Lower Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Name H'80 H'81 H'82 H'83 H'84 H'85 H'86 LVDCR LVDE — VINTDSEL VINTUSEL LVDSL LVDRE LVDDE LVDUE...
Page 562 Upper Address: H'FF Bit Names Lower Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Name H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 STOP CKS1 CKS0 SCI3 H'A9 BRR7 BRR6...
Page 563 Upper Address: H'FF Bit Names Lower Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Name H'C0 LPCR DTS1 DTS0 — SGS3 SGS2 SGS1 SGS0 LCD controller/ driver H'C1 —...
Page 564 Upper Address: H'FF Bit Names Lower Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Name H'E0 PUCR1 PUCR17 PUCR16 — PUCR14 PUCR13 — — — I/O port H'E1 PUCR3 PUCR37 PUCR36...
Page 565: Functions
Functions Address to which the register is mapped. Register name When displayed with two-digit number, this indicates the lower address, Register acronym and the upper address is HFF. Name of on-chip supporting module H'B6 Timer F TCRFTimer Control Register F Bit numbers Initial bit values TOLH...
Page 566 FLMCR1—Flash Memory Control Register 1 H'F020 Flash Memory  Initial value  Read/Write Program 0 Program mode cleared (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 and PSU = 1 Erase 0 Erase mode cleared (initial value) 1 Transition to erase mode [Setting condition] When SWE = 1 and ESU = 1...
Page 567 FLMCR2—Flash Memory Control Register 2 H'F021 Flash Memory        FLER Initial value        Read/Write Flash memory error Note: A write to FLMCR2 is prohibited. FLPWCR—Flash Memory Power Control Register H'F022 Flash Memory ...
Page 568 EBR—Erase Block Register H'F023 Flash Memory    Initial value    Read/Write Blocks 4 to 0 0 When a block of EB4 to EB0 is not selected (initial value) 1 When a block of EB4 to EB0 is selected Note: Set the bit of EBR to H'00 when erasing.
Page 569 LVDCR—Low-Voltage Detection Control Register H'86 LVDC Note: This register is implemented on the H8/38124 Group only.  LVDE VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE Initial value Read/Write Voltage Rise Interrupt Enable 0 Voltage rise interrupt requests disabled (initial value) 1 Voltage rise interrupt requests enabled Voltage Drop Interrupt Enable 0 Voltage drop interrupt requests disabled (initial value) 1 Voltage drop interrupt requests enabled...
Page 570 LVDSR—Low-Voltage Detection Status Register H'87 LVDC Note: This register is implemented on the H8/38124 Group only.     VREFSEL LVDDF LVDUF Initial value Read/Write LVD Power Supply Voltage Rise Flag 0 [Clearing condition] (initial v alue) When 0 is written after reading 1 1 [Setting condition] When the power supply voltage drops below Vint(D) while the LVDUE bit in LVDCR is set...
Page 571 ECPWCRH—Event Counter PWM Compare Register H H'8C ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value Sets event counter PWM waveform conversion period ECPWCRL—Event Counter PWM Compare Register L H'8D ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 Initial value Sets event counter PWM waveform conversion period ECPWDRH—Event Counter PWM Data Register H H'8E...
Page 572 WEGR—Wakeup Edge Select Register H'90 System Control WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value Read/Write WKPn Edge Selected WKPn pin falling edge detected WKPn pin rising edge detected (n = 7 to 0) Rev. 6.00, 08/04, page 542 of 628...
Page 573 SPCR—Serial Port Control Register H'91 SCI3      SPC32 SCINV3 SCINV2    Initial value   Read/Write Pin Input Data Inversion Switch input data is not inverted input data is inverted Pin Output Data Inversion Switch output data is not inverted output data is inverted /TXD...
Page 574 AEGSR—Input Pin Edge Select Register H'92  AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME Initial value Read/Write Event Counter PWM Enable/Disable, IRQAEC Select/Deselect AEC PWM halted, IRQAEC selected AEC PWM operation enabled, IRQAEC deselected IRQAEC Edge Select Bit 3 Bit 2 Description AIEGS1 AIEGS0...
Page 575 ECCR—Event Counter Control Register H'94  ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 Initial value Read/Write Event Counter PWM Clock Select Bit 3 Bit 2 Bit 1 Description PWCK2 PWCK1 PWCK0 φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 *: Don't care AEC Clock Select L Bit 5 Bit 4...
Page 576 ECCSR—Event Counter Control/Status Register H'95  CUEH CUEL CRCH CRCL Initial value Read/Write Counter Reset Control L ECL is reset ECL reset is cleared and count-up function is enabled Counter Reset Control H ECH is reset ECH reset is cleared and count-up function is enabled Count-up Enable L ECL event clock input is disabled.
Page 577 ECH—Event Counter H H'96 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value Read/Write Count value Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (EC). ECL—Event Counter L H'97 ECL7 ECL6...
Page 578 SMR—Serial Mode Register H'A8 SCI3 STOP CKS1 CKS0 Initial value Read/Write Clock Select φ clock φ w /2 clock φ/16 clock φ/64 clock Multiprocessor Mode Multiprocessor communication function disabled Multiprocessor communication function enabled Stop Bit Length 1 stop bit 2 stop bits Parity Mode Even parity Odd parity...
Page 579 BRR—Bit Rate Register H'A9 SCI3 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value Read/Write Serial transmit/receive bit rate Rev. 6.00, 08/04, page 549 of 628...
Page 580 SCR3—Serial Control Register 3 H'AA SCI3 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Description Bit 1 Bit 0 CKE1 CKE0 Communication Mode Clock Source Pin Function Asynchronous Internal clock I/O port Synchronous Internal clock Serial clock output Asynchronous Internal clock Clock output Synchronous...
Page 581 TDR—Transmit Data Register H'AB SCI3 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value Read/Write Data for transfer to TSR Rev. 6.00, 08/04, page 551 of 628...
Page 582 SSR—Serial Status Register H'AC SCI3 TDRE RDRF TEND MPBR MPBT Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Multiprocessor Bit Transfer A 0 multiprocessor bit is transmitted A 1 multiprocessor bit is transmitted Multiprocessor Bit Receive Data in which the multiprocessor bit is 0 has been received Data in which the multiprocessor bit is 1 has been received Transmit End...
Page 583 RDR—Receive Data Register H'AD SCI3 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value Read/Write Serial receiving data are stored TMA—Timer Mode Register A H'B0 Timer A     TMA3 TMA2 TMA1 TMA0    Initial value ...
Page 584 TCA—Timer Counter A H'B1 Timer A TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value Read/Write Count value Rev. 6.00, 08/04, page 554 of 628...
Page 585 TCSRW—Timer Control/Status Register W H'B2 Watchdog Timer B6WI TCWE B4WI TCSRWE B2WI WDON BOWI WRST Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Watchdog Timer Reset Clearing conditions: Reset by RES pin When TCSRWE = 1, and 0 is written in both B0WI and WRST Setting condition: When TCW overflows and an internal...
Page 586 TCW—Timer Counter W H'B3 Watchdog Timer TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value Read/Write Count value TMC—Timer Mode Register C H'B4 Timer C   TMC7 TMC6 TMC5 TMC2 TMC1 TMC0 Initial value   Read/Write Clock Select Internal clock: φ/8192 0 0 0 Internal clock: φ/2048...
Page 587 TCC—Timer Counter C H'B5 Timer C TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value Read/Write Count value Note: TCC is allocated to the same address as TLC. In a read, the TCC value is returned. TLC—Timer Load Register C H'B5 Timer C TLC7...
Page 588 TCRF—Timer Control Register F H'B6 Timer F TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value Read/Write Clock Select L Counting on external event (TMIF) Except rising/falling edge for 11 Do not specify this combination Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φ...
Page 589 TCSRF—Timer Control/Status Register F H'B7 Timer F OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Counter Clear L TCFL clearing by compare match is disabled TCFL clearing by compare match is enabled Timer Overflow Interrupt Enable L TCFL overflow interrupt request is disabled TCFL overflow interrupt request is enabled...
Page 590 TCFH—8-Bit Timer Counter FH H'B8 Timer F TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value Read/Write Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF). TCFL—8-Bit Timer Counter FL H'B9 Timer F...
Page 591 OCRFL—Output Compare Register FL H'BB Timer F OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value Read/Write Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). Rev.
Page 592 TMG—Timer Mode Register G H'BC Timer G OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Initial value R/(W) * R/(W) * Read/Write Clock Select Internal clock: counting on φ/64 1 Internal clock: counting on φ/32 1 0 Internal clock: counting on φ/2 1 Internal clock: counting on φ...
Page 593 ICRGF—Input Capture Register GF H'BD Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR H'BE Timer G ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0...
Page 594 LPCR—LCD Port Control Register H'C0 LCD Controller/Driver  DTS1 DTS0 SGS3 SGS2 SGS1 SGS0  Initial value Read/Write Segment Driver Select Function of Pins SEG to SEG Bit 3 Bit 2 Bit 1 Bit 0 Note SGS3 SGS2 SGS1 SGS0 Port Port Port...
Page 595 LCR—LCD Control Register H'C1 LCD Controller/Driver  DISP CKS3 CKS2 CKS1 CKS0 Initial value  Read/Write Frame Frequency Select Bit 2 Bit 1 Bit 1 Bit 3 Operating Clock CKS2 CKS3 CKS1 CKS0 φ w φ w /2 φ w /4 φ/2 φ/4 φ/8...
Page 596 LCR2—LCD Control Register 2 H'C2    LCDAB CDS3 CDS2 CDS1 CDS0  Initial value   Read/Write A Waveform/B Waveform Switching Control 0 Drive using A waveform 1 Drive using B waveform Removal of Split-Resistance Control CDS3 CDS2 CDS1 CDS0 Split-resistance condition...
Page 597 AMR—A/D Mode Register H'C6 A/D Converter   TRGE Initial value   Read/Write Channel Select Bit 3 Bit 2 Bit 1 Bit 0 Analog Input Channel No channel selected Do not specify this combination *: Don't care External Trigger Select 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG...
Page 598 ADRRH—A/D Result Register H H'C4 A/D Converter ADRRL—A/D Result Register L H'C5 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write A/D conversion result ADRRL     ...
Page 599 PMR1—Port Mode Register 1 H'C8 I/O Port      IRQ3 IRQ4 TMIG    Initial value   Read/Write /TMIG Pin Function Switch 0 Functions as P1 I/O pin 1 Functions as TMIG input pin /IRQ /ADTRG Pin Function Switch 0 Functions as P1 I/O pin...
Page 600 PMR2—Port Mode Register 2 H'C9 I/O Port     POF1 WDCKS IRQ0 Initial value     Read/Write /IRQ0 Pin Function Switch 0 Functions as P4 I/O pin 1 Functions as IRQ input pin TMIG Noise Canceller Select 0 Noise cancellation function not used 1 Noise cancellation function used Watchdog Timer Switch...
Page 601 PMR3—Port Mode Register 3 H'CA I/O Port    AEVL AEVH TMOFH TMOFL    Initial value Read/Write /UD Pin Function Switch 0 Functions as P3 I/O pin 1 Functions as UD input pin /TMOFL Pin Function Switch 0 Functions as P3 I/O pin 1 Functions as TMOFL output pin...
Page 602 PMR5—Port Mode Register 5 H'CC I/O Port Initial value Read/Write /WKP /SEG Pin Function Switch 0 Functions as P5 I/O pin 1 Functions as WKP input pin (n = 7 to 0) PWCR2—PWM2 Control Register H'CD 10-Bit PWM   ...
Page 603 PWDRU2—PWM2 Data Register U H'CE 10-Bit PWM       PWDRU21 PWDRU20 Initial value       Read/Write Upper 2 bits of PWM2 waveform generation data PWDRL2—PWM2 Data Register L H'CF 10-Bit PWM PWDRL27 PWDRL26 PWDRL25 PWDRL24...
Page 604 PWCR1—PWM1 Control Register H'D0 10-Bit PWM      PWCR12 PWCR11 PWCR10 Initial value      Read/Write Clock Select 0 The input clock is φ (tφ * = 1/φ) The conversion period is 512/φ, with a minimum modulation width of 1/2φ The input clock is φ/2 (tφ...
Page 605 PWDRU1—PWM1 Data Register U H'D1 10-Bit PWM       PWDRU11 PWDRU10 Initial value       Read/Write Upper 2 bits of data for generating PWM1 waveform PWDRL1—PWM1 Data Register L H'D2 10-Bit PWM PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13...
Page 606 PDR4—Port Data Register 4 H'D7 I/O Ports     Initial value     Read/Write Data for port 4 pins Reads P4 state PDR5—Port Data Register 5 H'D8 I/O Ports Initial value Read/Write Data for port 5 pins PDR6—Port Data Register 6 H'D9 I/O Ports...
Page 607 PDR8—Port Data Register 8 H'DB I/O Ports Initial value Read/Write Data for port 8 pins PDR9—Port Data Register 9 H'DC I/O Ports   Initial value   Read/Write Data for port 9 pins PDRA—Port Data Register A H'DD I/O Ports ...
Page 608 PUCR1—Port Pull-Up Control Register 1 H'E0 I/O Ports     PUCR1 PUCR1 PUCR1 PUCR1     Initial value Read/Write Port 1 Input Pull-up MOS Control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR1 specification is 0. (Input port specification) Note: * PUCR1 is not equipped with H8/38124 Group.
Page 609 PUCR5—Port Pull-Up Control Register 5 H'E2 I/O Ports PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 PUCR5 Initial value Read/Write Port 5 Input Pull-up MOS Control Input pull-up MOS is off Input pull-up MOS is on Note: When the PCR5 specification is 0. (Input port specification) PUCR6—Port Pull-Up Control Register 6 H'E3...
Page 610 PCR3—Port Control Register 3 H'E6 I/O Ports PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 PCR3 Initial value Read/Write Port 3 Input/Output Select 0 Input pin 1 Output pin PCR4—Port Control Register 4 H'E7 I/O Ports      PCR4 PCR4 PCR4...
Page 611 PCR6—Port Control Register 6 H'E9 I/O Ports PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 PCR6 Initial value Read/Write Port 6 Input/Output Select 0 Input pin 1 Output pin PCR7—Port Control Register 7 H'EA I/O Ports PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7 PCR7...
Page 612 PMR9—Port Mode Register 9 H'EC I/O Ports PIOFF/ *      PWM2 PWM1  Initial value     Read/Write P90/PWM1 Pin Function Switch Functions as P90 output pin Functions as PWM1 output pin P91/PWM2 Pin Function Switch Functions as P91 output pin Functions as PWM2 output pin P92 to P90 Step-up Circuit Control...
Page 613 PCRA—Port Control Register A H'ED I/O Ports     PCRA PCRA PCRA PCRA Initial value     Read/Write Port A Input/Output Select 0 Input pin 1 Output pin PMRB—Port Mode Register B H'EE I/O Ports  ...
Page 614 SYSCR1—System Control Register 1 H'F0 System Control  SSBY STS2 STS1 STS0 LSON Initial value  Read/Write Active (medium-speed) Mode Clock Select φ φ φ φ /128 Low Speed on Flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ...
Page 615 SYSCR2—System Control Register 2 H'F1 System Control    NESEL DTON MSON Initial value    Read/Write Subactive Mode Clock Select φ φ φ Medium Speed on Flag *: Don't care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct Transfer on Flag 0 •...
Page 616 IEGR—IRQ Edge Select Register H'F2 System Control     IEG4 IEG3 IEG1 IEG0  Initial value    Read/Write Edge Select 0 Falling edge of IRQ pin input is detected Rising edge of IRQ pin input is detected Edge Select 0 Falling edge of IRQ , TMIC pin input is detected...
Page 617 IENR1—Interrupt Enable Register 1 H'F3 System Control  IENTA IENWP IEN4 IEN3 IENEC2 IEN1 IEN0  Initial value Read/Write to IRQ Interrupt Enable 0 Disables IRQ to IRQ interrupt, requests Enables IRQ to IRQ interrupt requests IRQAEC Interrupt Enable 0 Disables IRQAEC interrupt requests Enables IRQAEC interrupt requests and IRQ Interrupt Enable...
Page 618 IENR2—Interrupt Enable Register 2 H'F4 System Control  IENDT IENAD IENTG IENTFH IENTFL IENTC IENEC  Initial value Read/Write Asynchronous Event Counter Interrupt Enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C Interrupt Enable 0 Disables timer C interrupt requests 1 Enables timer C interrupt requests Timer FL Interrupt Enable...
Page 619 OSCCR—Clock Pulse Generator Control Register H'F5 Clock Pulse Generator Note: This register is implemented on the H8/38124 Group only.      SUBSTP IRQAECF OSCF   Initial value Read/Write OSC Flag 0 Operation using system clock oscillator (on-chip oscillator stopped) 1 Operation using on-chip oscillator (system clock oscillator stopped) IRQAEC Flag 0 IRQAEC pin set to GND during resets...
Page 620 IRR1—Interrupt Request Register 1 H'F6 System Control   IRRTA IRRI4 IRRI3 IRREC2 IRRI1 IRRI0  Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *  Read/Write IRQ1 and IRQ0 Interrupt Request Flags 0 Clearing condition: When IRRIn = 1, it is cleared by writing 0 1 Setting condition: When pin IRQn is designated for interrupt...
Page 621 IRR2—Interrupt Request Register 2 H'F7 System Control  IRRDT IRRAD IRRTG IRRTFH IRRTFL IRRTC IRREC  Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Asynchronous Event Counter Interrupt Request Flag 0 Clearing condition: When IRREC = 1, it is cleared by writing 0 1 Setting condition: When the asynchronous event counter value...
Page 622 TMW—Timer Mode Register W H'F8 Watchdog Timer Note: This register is implemented on the H8/38124 Group only.     CKS3 CKS2 CKS1 CKS0 Initial value     Read/Write Internal Clock Select CDS3 CDS2 CDS1 CDS0 Clock source φ/64 φ/128 φ/256...
Page 623 IWPR—Wakeup Interrupt Request Register H'F9 System Control IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write Wakeup Interrupt Request Register 0 Clearing condition: When IWPFn = 1, it is cleared by writing 0 1 Setting condition: When pin WKPn is designated for wakeup input and a...
Page 624 CKSTPR1—Clock Stop Register 1 H'FA System Control   S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value   Read/Write Timer A Module Standby Mode Control 0 Timer A is set to module standby mode Timer A module standby mode is cleared Timer C Module Standby Mode Control 0 Timer C is set to module standby mode Timer C module standby mode is cleared...
Page 625 CKSTPR2—Clock Stop Register 2 H'FB System Control   LVDCKSTP* PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value   Read/Write LCD Module Standby Mode Control 0 LCD is set to module standby mode LCD module standby mode is cleared PWM1 Module Standby Mode Control 0 PWM1 is set to module standby mode PWM1 module standby mode is cleared WDT Module Standby Mode Control...
Page 626: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Block Diagrams of Port 1 SBY (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 7 and 4 m = 4 and 3...
Page 627 SBY (low level during reset and in standby mode) PUCR1 PMR1 PDR1 PCR1 PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1(b) Port 1 Block Diagram (Pin P1 , Products other than H8/38124 Group) Rev.
Page 628 PUCR1 PMR1 PDR1 PCR1 Timer G module TMIG PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1(c) Port 1 Block Diagram (Pin P1 Rev. 6.00, 08/04, page 598 of 628...
Page 629: Block Diagrams Of Port 3
Block Diagrams of Port 3 PUCR3 PMR3 PDR3 PCR3 AEC module AEVH(P3 AEVL(P3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 7 and 6 Figure C.2(a) Port 3 Block Diagram (Pins P3 and P3 Rev.
Page 630 PUCR3 PMR2 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 PMR2 Port mode register 2 Figure C.2(b) Port 3 Block Diagram (Pin P3 Rev. 6.00, 08/04, page 600 of 628...
Page 631 PUCR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 n = 4 and 3 Figure C.2(c) Port 3 Block Diagram (Pins P3 and P3 Rev. 6.00, 08/04, page 601 of 628...
Page 632 TMOFH (P3 TMOFL (P3 PUCR3 PMR3 PDR3 PCR3 PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 2 and 1 Figure C.2(d) Port 3 Block Diagram (Pins P3 and P3 Rev.
Page 633 PUCR3 PMR3 PDR3 PCR3 Timer C module PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.2(e) Port 3 Block Diagram (Pin P3 Rev. 6.00, 08/04, page 603 of 628...
Page 634: Block Diagrams Of Port 4
Block Diagrams of Port 4 PMR2 PMR2: Port mode register 2 Figure C.3(a) Port 4 Block Diagram (Pin P4 Rev. 6.00, 08/04, page 604 of 628...
Page 635 SCINV3 SPC32 SCI3 module TXD32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(b) Port 4 Block Diagram (Pin P4 Rev. 6.00, 08/04, page 605 of 628...
Page 636 SCI3 module RE32 RXD32 PDR4 PCR4 SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(c) Port 4 Block Diagram (Pin P4 Rev. 6.00, 08/04, page 606 of 628...
Page 637 SCI3 module SCKIE32 SCKOE32 SCKO32 SCKI32 PDR4 PCR4 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(d) Port 4 Block Diagram (Pin P4 Rev. 6.00, 08/04, page 607 of 628...
Page 638: Block Diagram Of Port 5
Block Diagram of Port 5 SBY * PUCR5 PMR5 PDR5 PCR5 PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 Note: * The value of SBY is fixed at 1 in the HD64F38024. PUCR5: Port pull-up control register 5 n = 7 to 0 Figure C.4 Port 5 Block Diagram Rev.
Page 639: Block Diagram Of Port 6
Block Diagram of Port 6 PUCR6 PDR6 PCR6 PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.5 Port 6 Block Diagram Rev. 6.00, 08/04, page 609 of 628...
Page 640: Block Diagram Of Port 7
Block Diagram of Port 7 PDR7 PCR7 PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.6 Port 7 Block Diagram Rev. 6.00, 08/04, page 610 of 628...
Page 641: Block Diagram Of Port 8
Block Diagram of Port 8 PDR8 PCR8 PDR8: Port data register 8 PCR8: Port control register 8 n = 7 to 0 Figure C.7 Port 8 Block Diagram Rev. 6.00, 08/04, page 611 of 628...
Page 642: Block Diagrams Of Port 9
Block Diagrams of Port 9 PWM module PMR9 PDR9 PDR9: Port data register 9 n = 1 and 0 Figure C.8(a) Port 9 Block Diagram (Pins P9 and P9 PDR9 PDR9: Port data register 9 n = 5 to 2 Figure C.8(b) Port 9 Block Diagram (Pins P9 to P9 Rev.
Page 643: Block Diagram Of Port A
Block Diagram of Port A PDRA PCRA PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.9 Port A Block Diagram Rev. 6.00, 08/04, page 613 of 628...
Page 644: Block Diagram Of Port B
C.10 Block Diagram of Port B Internal data bus A/D module AMR3 to AMR0 n = 7 to 0 Figure C.10 Port B Block Diagram Rev. 6.00, 08/04, page 614 of 628...
Page 645: Appendix D Port States In The Different Processing States
Appendix D Port States in the Different Processing States Table D.1 Port States Overview Port Reset Sleep Subsleep Standby Watch Subactive Active High Retained Retained High Retained Functions Functions impedance * impedance High Retained Retained High Retained Functions Functions impedance * impedance High Retained...
Page 646: Appendix E List Of Product Codes
Appendix E List of Product Codes Table E.1 H8/38024 Group Product Code Lineup Package Product Type Product Code Mark Code (Package Code) H8/38024 H8/38024 Mask ROM Regular HD64338024H HD64338024(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338024F HD64338024(***)F 80-pin QFP (FP-80B)
Page 647 Package Product Type Product Code Mark Code (Package Code) H8/38024 H8/38022 Mask ROM Regular HD64338022H HD64338022(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338022F HD64338022(***)F 80-pin QFP (FP-80B) HD64338022W HD64338022(***)W 80-pin TQFP (TFP-80C) HCD64338022 — Wide-range HD64338022D HD64338022(***)H 80-pin QFP (FP-80A)
Page 648 Package Product Type Product Code Mark Code (Package Code) H8/38024S H8/38021S Mask ROM Regular HD64338021SH HD64338021(***)H 80-pin QFP (FP-80A) Group versions specifications HD64338021SW HD64338021(***)W 80-pin TQFP (TFP-80C) HD64338021SLPV 338021S(***)LPV 85-pin TFLGA (TLP-85V) HCD64338021S — Wide-range HD64338021SD HD64338021(***)H 80-pin QFP (FP-80A) specifications HD64338021SWI HD64338021(***)W...
Page 649: Appendix F Package Dimensions
Appendix F Package Dimensions Dimensional drawings of the H8/38024 Group, H8/38024S Group, and H8/38124 Group packages FP-80A, FP-80B, and TFP-80C are shown in figures F.1, F.2, and F.3 below. 17.2 ± 0.3 Unit: mm * 0.32 ± 0.08 0.12 M 0.30 ±...
Page 650 24.8 ± 0.4 Unit: mm * 0.37 ± 0.08 0.15 M 0.35 ± 0.06 0° − 10° 1.2 ± 0.2 0.15 Package Code FP-80B  JEDEC  * Dimension including the plating thickness JEITA Mass (reference value) 1.7 g Base material dimension Figure F.2 FP-80B Package Dimensions Rev.
Page 651 14.0 ± 0.2 Unit: mm 0.22 ± 0.05 0.10 0.20 ± 0.04 1.25 0° − 8° 0.5 ± 0.1 0.10 Package Code TFP-80C  JEDEC * Dimension including the plating thickness JEITA Conforms Base material dimension Mass (reference value) 0.4 g Figure F.3 TFP-80C Package Dimensions Rev.
Page 652 Unit: mm 0.20 C A 4 × 0.15 0.65 0.575 85 × φ0.35 ± 0.05 φ0.08 0.10 C (Flatness of land portion) Figure F.4 TLP-85V Package Dimensions Rev. 6.00, 08/04, page 622 of 628...
Page 653: Appendix G Specifications Of Chip Form
Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure G.1. The specifications of the chip form of the HCD64F38024 and HCD64F38024R are shown in figure G.2. The specifications of the chip form of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure G.3.
Page 654 X-direction: 2.91 ± 0.05 Y-direction: 2.91 ± 0.05 X-direction: 2.91 ± 0.25 Maximum plain Y-direction: 2.91 ± 0.25 Unit: mm Figure G.3 Chip Sectional Figure of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev. 6.00, 08/04, page 624 of 628...
Page 655: Appendix H Form Of Bonding Pads
Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, HCD64338020, HCD64F38024, HCD64F38024R, HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure H.1. Bonding area Metal layer 72 mm 5 mm Figure H.1 Bonding Pad Form Rev.
Page 656: Appendix I Specifications Of Chip Tray
Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure I.1. The specifications of the chip tray for the HCD64F38024 and HCD64F38024R are shown in figure I.2. The specifications of the chip tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure I.3.
Page 657 Chip direction Chip Type name 3.84 Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT015 Carved code: TCT45-060P 4.5 ± 0.05 6.2 ± 0.1 6.9 ± 0.1 Unit: mm X-X' cross section Figure I.2 Specifications of Chip Tray for the HCD64F38024 and HCD64F38024R Rev.
Page 658 Chip direction Type name Chip 2.91 Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT022 Carved code: TCT036036-060 3.6 ± 0.05 4.48 ± 0.1 5.34 ± 0.1 Unit: mm X-X' cross section Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev.
Page 659 Publication Date: 1st Edition, November 2000 Rev.6.00, August 27, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.  2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 660 Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd.
Page 661 H8/38024, H8/38024S, H8/38024F-ZTAT, H8/38124 Group Hardware Manual...

This manual is also suitable for:

H8/38024f-ztat H8/38124 H8/38024s

Renesas H8/38024 Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 Exception Handling

Section 4 Clock Pulse Generators

Section 5 Power-Down Modes

Section 6 ROM

Section 7 RAM

Section 8 I/O Ports

Section 9 Timers

Section 10 Serial Communication Interface

Section 11 10-Bit PWM

Section 12 A/D Converter

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