Renesas H8/3847R Series Hardware Manual page 321

Bit 5: Timer overflow interrupt enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH Description
0 TCFH overflow interrupt request is disabled
1 TCFH overflow interrupt request is enabled
Bit 4: Counter clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH Description
0 16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1 16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3: Timer overflow flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL Description
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCFL overflows from H'FF to H'00
Rev. 6.00 Aug 04, 2006 page 283 of 680
Section 9 Timers
(initial value)
(initial value)
(initial value)
REJ09B0145-0600