Table 9.10 Timer F Operation Modes - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power
Table of Contents

Advertisement

Section 9 Timers
4. TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
5. Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare Match Flag set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F Operation Modes
Timer F operation modes are shown in table 9.10.

Table 9.10 Timer F Operation Modes

Operation
Mode
Reset
TCF
Reset
OCRF
Reset
TCRF
Reset
TCSRF
Reset
* When φ
Note:
/4 is selected as the TCF internal clock in active mode or sleep mode, since
w
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φ
/4 must be selected as the internal clock. The counter will not operate if any
w
other internal clock is selected.
Rev. 6.00 Aug 04, 2006 page 290 of 680
REJ09B0145-0600
Active
Sleep
Functions
Functions
Functions
Held
Functions
Held
Functions
Held
Watch
Subactive Subsleep Standby
Functions/
Functions/
Halted*
Halted*
Held
Functions
Held
Functions
Held
Functions
Functions/
Halted
Halted*
Held
Held
Held
Held
Held
Held
Module
Standby
Halted
Held
Held
Held

Advertisement

Table of Contents
loading

Table of Contents